test_pll.vhd

VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_pll is
end test_pll;

architecture test_pll_a of test_pll is
    component pll is
        port(clk_in,data_in : in  std_logic;
             clk_out         : out std_logic;
	          state           : out std_logic;
	          data_out        : out std_logic);
    end component pll;
   
    signal data_in  :std_logic :='0';
    signal clk_in   :std_logic :='0';
    signal clk_out  :std_logic;
    signal state    :std_logic;
    signal data_out :std_logic;
begin 
    u : pll port map(clk_in,data_in,clk_out,state,data_out);
   
        process(clk_in)
    begin
        clk_in <= not clk_in after 0.020833333333333333333333 us;
    end process;

    process(data_in)
    begin
        data_in <= not data_in after 15.625 us;
    end process;

end architecture test_pll_a;