lpc22xx.h

LPC Flash Programming Routines for LPC21

/******************************************************************************
 *
 * $RCSfile: $
 * $Revision: $
 *
 * Header file for Philips LPC22xx ARM Processors 
 * Copyright 2004 R O SoftWare
 *
 * No guarantees, warrantees, or promises, implied or otherwise.
 * May be used for hobby or commercial purposes provided copyright
 * notice remains intact.
 *
 *****************************************************************************/
#ifndef INC_LPC22xx_H
#define INC_LPC22xx_H

#define REG_8           volatile unsigned char
#define REG16           volatile unsigned short
#define REG32           volatile unsigned long

#include "lpc2100/lpcWD.h"
#include "lpc2100/lpcTMR.h"
#include "lpc2100/lpcUART.h"
#include "lpc2100/lpcI2C.h"
#include "lpc2100/lpcSPI.h"
#include "lpc2100/lpcRTC.h"
#include "lpc2100/lpcGPIO.h"
#include "lpc2100/lpcPIN.h"
#include "lpc2100/lpcADC.h"
#include "lpc2100/lpcSCB.h"
#include "lpc2100/lpcEMC.h"
#include "lpc2100/lpcVIC.h"

///////////////////////////////////////////////////////////////////////////////
// Watchdog
#define WD              ((wdRegs_t *)0xE0000000)

// Watchdog Registers
#define WDMOD           WD->mod         /* Watchdog Mode Register */
#define WDTC            WD->tc          /* Watchdog Time Constant Register */
#define WDFEED          WD->feed        /* Watchdog Feed Register */
#define WDTV            WD->tv          /* Watchdog Time Value Register */

///////////////////////////////////////////////////////////////////////////////
// Timer 0
#define TMR0            ((pwmTmrRegs_t *)0xE0004000)

// Timer 0 Registers
#define T0IR            TMR0->ir        /* Interrupt Register */
#define T0TCR           TMR0->tcr       /* Timer Control Register */
#define T0TC            TMR0->tc        /* Timer Counter */
#define T0PR            TMR0->pr        /* Prescale Register */
#define T0PC            TMR0->pc        /* Prescale Counter Register */
#define T0MCR           TMR0->mcr       /* Match Control Register */
#define T0MR0           TMR0->mr0       /* Match Register 0 */
#define T0MR1           TMR0->mr1       /* Match Register 1 */
#define T0MR2           TMR0->mr2       /* Match Register 2 */
#define T0MR3           TMR0->mr3       /* Match Register 3 */
#define T0CCR           TMR0->ccr       /* Capture Control Register */
#define T0CR0           TMR0->cr0       /* Capture Register 0 */
#define T0CR1           TMR0->cr1       /* Capture Register 1 */
#define T0CR2           TMR0->cr2       /* Capture Register 2 */
#define T0CR3           TMR0->cr3       /* Capture Register 3 */
#define T0EMR           TMR0->emr       /* External Match Register */

///////////////////////////////////////////////////////////////////////////////
// Timer 1
#define TMR1            ((pwmTmrRegs_t *)0xE0008000)

// Timer 1 Registers
#define T1IR            TMR1->ir        /* Interrupt Register */
#define T1TCR           TMR1->tcr       /* Timer Control Register */
#define T1TC            TMR1->tc        /* Timer Counter */
#define T1PR            TMR1->pr        /* Prescale Register */
#define T1PC            TMR1->pc        /* Prescale Counter Register */
#define T1MCR           TMR1->mcr       /* Match Control Register */
#define T1MR0           TMR1->mr0       /* Match Register 0 */
#define T1MR1           TMR1->mr1       /* Match Register 1 */
#define T1MR2           TMR1->mr2       /* Match Register 2 */
#define T1MR3           TMR1->mr3       /* Match Register 3 */
#define T1CCR           TMR1->ccr       /* Capture Control Register */
#define T1CR0           TMR1->cr0       /* Capture Register 0 */
#define T1CR1           TMR1->cr1       /* Capture Register 1 */
#define T1CR2           TMR1->cr2       /* Capture Register 2 */
#define T1CR3           TMR1->cr3       /* Capture Register 3 */
#define T1EMR           TMR1->emr       /* External Match Register */

///////////////////////////////////////////////////////////////////////////////
// Pulse Width Modulator (PWM)
#define PWM             ((pwmTmrRegs_t *)0xE0014000)

// PWM Registers
#define PWMIR           PWM->ir         /* Interrupt Register */
#define PWMTCR          PWM->tcr        /* Timer Control Register */
#define PWMTC           PWM->tc         /* Timer Counter */
#define PWMPR           PWM->pr         /* Prescale Register */
#define PWMPC           PWM->pc         /* Prescale Counter Register */
#define PWMMCR          PWM->mcr        /* Match Control Register */
#define PWMMR0          PWM->mr0        /* Match Register 0 */
#define PWMMR1          PWM->mr1        /* Match Register 1 */
#define PWMMR2          PWM->mr2        /* Match Register 2 */
#define PWMMR3          PWM->mr3        /* Match Register 3 */
#define PWMMR4          PWM->mr4        /* Match Register 4 */
#define PWMMR5          PWM->mr5        /* Match Register 5 */
#define PWMMR6          PWM->mr6        /* Match Register 6 */
#define PWMPCR          PWM->pcr        /* Control Register */
#define PWMLER          PWM->ler        /* Latch Enable Register */

///////////////////////////////////////////////////////////////////////////////
// Universal Asynchronous Receiver Transmitter 0 (UART0)
#define UART0           ((uartRegs_t *)0xE000C000)
#define U0_PINSEL       (0x00000005)    /* PINSEL0 Value for UART0 */
#define U0_PINMASK      (0x0000000F)    /* PINSEL0 Mask for UART0 */

// UART0 Registers
#define U0RBR           UART0->rbr      /* Receive Buffer Register */
#define U0THR           UART0->thr      /* Transmit Holding Register */
#define U0IER           UART0->ier      /* Interrupt Enable Register */
#define U0IIR           UART0->iir      /* Interrupt ID Register */
#define U0FCR           UART0->fcr      /* FIFO Control Register */
#define U0LCR           UART0->lcr      /* Line Control Register */
#define U0LSR           UART0->lsr      /* Line Status Register */
#define U0SCR           UART0->scr      /* Scratch Pad Register */
#define U0DLL           UART0->dll      /* Divisor Latch Register (LSB) */
#define U0DLM           UART0->dlm      /* Divisor Latch Register (MSB) */

///////////////////////////////////////////////////////////////////////////////
// Universal Asynchronous Receiver Transmitter 1 (UART1)
#define UART1           ((uartRegs_t *)0xE0010000)
#define U1_PINSEL       (0x00050000)    /* PINSEL0 Value for UART1 */
#define U1_PINMASK      (0x000F0000)    /* PINSEL0 Mask for UART1 */

// UART1 Registers
#define U1RBR           UART1->rbr      /* Receive Buffer Register */
#define U1THR           UART1->thr      /* Transmit Holding Register */
#define U1IER           UART1->ier      /* Interrupt Enable Register */
#define U1IIR           UART1->iir      /* Interrupt ID Register */
#define U1FCR           UART1->fcr      /* FIFO Control Register */
#define U1LCR           UART1->lcr      /* Line Control Register */
#define U1MCR           UART1->mcr      /* MODEM Control Register */
#define U1LSR           UART1->lsr      /* Line Status Register */
#define U1MSR           UART1->msr      /* MODEM Status Register */
#define U1SCR           UART1->scr      /* Scratch Pad Register */
#define U1DLL           UART1->dll      /* Divisor Latch Register (LSB) */
#define U1DLM           UART1->dlm      /* Divisor Latch Register (MSB) */

///////////////////////////////////////////////////////////////////////////////
// I2C Interface
#define I2C             ((i2cRegs_t *)0xE001C000)

// I2C Registers
#define I2CONSET        I2C->conset     /* Control Set Register */
#define I2STAT          I2C->stat       /* Status Register */
#define I2DAT           I2C->dat        /* Data Register */
#define I2ADR           I2C->adr        /* Slave Address Register */
#define I2SCLH          I2C->sclh       /* SCL Duty Cycle Register (high half word) */
#define I2SCLL          I2C->scll       /* SCL Duty Cycle Register (low half word) */
#define I2CONCLR        I2C->conclr     /* Control Clear Register */

///////////////////////////////////////////////////////////////////////////////
// Serial Peripheral Interface 0 (SPI0)
#define SPI0            ((spiRegs_t *)0xE0020000)

// SPI0 Registers
#define S0SPCR          SPI0->cr        /* Control Register */
#define S0SPSR          SPI0->sr        /* Status Register */
#define S0SPDR          SPI0->dr        /* Data Register */
#define S0SPCCR         SPI0->ccr       /* Clock Counter Register */
#define S0SPINT         SPI0->flag      /* Interrupt Flag Register */

///////////////////////////////////////////////////////////////////////////////
// Serial Peripheral Interface 1 (SPI1)
#define SPI1            ((spiRegs_t *)0xE0030000)