📄 pxa-gspi.c
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Module Name:
pxa-gspi.c
Abstract:
Holds implementation of pcmcia serial driver interface. This serial PDD
makes use of the ser16550 library to do most of the work.
Functions:
Notes:
--*/
#include <windows.h>
#include <nkintr.h>
#include <ndis.h>
#include <types.h>
#include <memory.h>
#include <tchar.h>
#include <ceddk.h>
#include <s3c2440a.h>
#include <Devload.h>
#include <giisr.h>
#include "myintr.h"
#include "pxa-gpio.h"
#include "pxa-ssp.h"
#include "pxa-dma.h"
#include "pxa-gspi.h"
#include "sspioctl.h"
#define RETAILMSG(cond,printf_exp) ((cond)?(NKDbgPrintfW printf_exp),1:0)
#define DEBUGMSG(cond,printf_exp) RETAILMSG(1,printf_exp)
#ifdef DEBUG
#define GSPIMSG DEBUGMSG
#else
#define GSPIMSG RETAILMSG
#endif ///DEBUG
#define ONEBIT 0x1
///int g_fmDnRdy = FALSE;
extern int g_spi_dummy_clk_reg;
extern int g_spi_dummy_clk_data;
#define DMA_DATASIZE 0 //0:data size=1, 1:data size=2,2:data size=4,
///volatile BULVERDE_DMA_REG *pg_DMARegs;
static LPCTSTR pg_szActiveKey = _T("GSPI8385");
///============================================================================
/// Flags to control the displayed message
#define ERRMSG 0 ///Error Message. Displayed only error occurred
#define FUNCTAG 0 ///Display the message to show the function enter/exit
#define TICKCNTMSG 0 ///Tick count message
#define PROGFLOW 0 ///Display the message to show the program's running flow
#define TX_FRAG 0 ///Display the message whenever the fragmentation is needed in TX
#define RX_FRAG 0 ///Display the message whenever the fragmentation is needed in RX
#define DMA_MSG 0 ///Display the message for debuggin the DMA module
///============================================================================
#define ENTERFUNC() GSPIMSG(FUNCTAG,(L"Enter %s\n", TEXT(__FUNCTION__)))
#define EXITFUNC(x) GSPIMSG(FUNCTAG, (L"Exit %s (%d)\n", TEXT(__FUNCTION__), x))
#define GSPI_MAX_REG_RETRY 3
static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
static GSPI_STATUS setup_read_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
///////////////////////////////////////////////////////////////////////////////
#if (SSPCTRLER == 1)
#define SSPREG_PHY_BASE BULVERDE_BASE_REG_PA_SSP1
#define DMA_CHMAP_SSP_RX DMA_CHMAP_SSP1_RX
#define DMA_CHMAP_SSP_TX DMA_CHMAP_SSP1_TX
#define XLLP_DMAC_SSP_RX XLLP_DMAC_SSP_1_RX
#define XLLP_DMAC_SSP_TX XLLP_DMAC_SSP_1_TX
#elif (SSPCTRLER == 2)
#define SSPREG_PHY_BASE BULVERDE_BASE_REG_PA_SSP2
#define DMA_CHMAP_SSP_RX DMA_CHMAP_SSP2_RX
#define DMA_CHMAP_SSP_TX DMA_CHMAP_SSP2_TX
#define XLLP_DMAC_SSP_RX XLLP_DMAC_SSP_2_RX
#define XLLP_DMAC_SSP_TX XLLP_DMAC_SSP_2_TX
#elif (SSPCTRLER == 3)
#define SSPREG_PHY_BASE BULVERDE_BASE_REG_PA_SSP3
#define DMA_CHMAP_SSP_RX DMA_CHMAP_SSP3_RX
#define DMA_CHMAP_SSP_TX DMA_CHMAP_SSP3_TX
#define XLLP_DMAC_SSP_RX XLLP_DMAC_SSP_3_RX
#define XLLP_DMAC_SSP_TX XLLP_DMAC_SSP_3_TX
#endif ///SSPCTRLER
///---------------------------------------------------------
///Signal Definition
///
#define SSP_SCLK 23
#define SSP_SFRM 24
#define SSP_TX 25
#define SSP_RX 26
#define SSP_INTR 22
#define SSPSCLK_ATTR GPIO_ALT_FN_2_OUT
#define SSPSFRM_ATTR GPIO_OUT
#define SSPTX_ATTR GPIO_ALT_FN_2_OUT
#define SSPRX_ATTR GPIO_ALT_FN_1_IN
#define SSPIRQ_ATTR GPIO_IN
///Define DMA channel
#define DMA_CH_READ 8
//#define DMA_CH_RW 24 //for PXA 27X
#define DMA_CH_RW 1 //for S2440
///#define SSP_IRQNUM 22///Trial value from sdhc_mainstoneii.reg
#define MVL_DEF_DRR 0x05
#define MVL_DEF_DRP 0x0e
///CLK dividend
static int clkdiv = 0;
///---------------------------------------------------------
///Buffer defintion
///
#define PXA_SSP_BLKSZ_MAX (1<<9)
#define PXA_SSP_BLOCKS_PER_BUFFER (4)
#define PXA_SSP_IODATA_SIZE (PXA_SSP_BLOCKS_PER_BUFFER * \
PXA_SSP_BLKSZ_MAX)
///---------------------------------------------------------
///DMA ISR functions
///
/// Maximum waiting period (us)
#define MAX_WAITus 10000000 //dralee 100ms
///#define MAX_WAITus 10000000 //dralee 100ms
// the dmcd struct is for documentation
struct dcmdRegBits
{
unsigned len :13;
unsigned rsv0 :1;
unsigned width :2;
unsigned size :2;
unsigned endian :1;
unsigned flybyt :1;
unsigned flybys :1;
unsigned endirqen :1;
unsigned startirqen :1;
unsigned rsv1 :5;
unsigned flowtrg :1;
unsigned flowsrc :1;
unsigned inctrgadd :1;
unsigned incsrcadd :1;
};
union DMACmdReg// allow bitfields or masks
{
volatile struct dcmdRegBits DcmdReg ;
volatile DWORD DcmdDword;
} ;
//#define DEFAULT_IST_PRIORITY 50
#define DEFAULT_IST_PRIORITY 101
///#define DEFAULT_IST_PRIORITY 249
///#define SSP_DMA_INTR (SYSINTR_FIRMWARE+1)
///#define SSP_DMA_INTR (SYSINTR_FIRMWARE+1)
///static ULONG dma_irqr(PSSP_HARDWARE_CONTEXT pHC);
///static ULONG dma_irqw(VOID* devid);
static BOOLEAN dma_ist(LPVOID param);
static BOOLEAN dev_ist(PSSP_HARDWARE_CONTEXT pHC);
static GSPI_STATUS ssp_write_data_direct(DWORD hDC, PWORD data, WORD reg, WORD nword);
static GSPI_STATUS ssp_read_data_direct(DWORD hDC, WORD* data, WORD reg, WORD nword, WORD dummy_clk);
void putcToSoc(PSSP_HARDWARE_CONTEXT pHC, UCHAR c);
void EnableEINT(PSSP_HARDWARE_CONTEXT pHC);
///---------------------------------------------------------
//The function was modified from XllpOstDelayMicroSeconds() in XLLP\xllp_ost.c
//
// OST Tick constants
//
#define XLLP_OST_TICKS_MS 3250 // 1ms in ticks (3.25x10^6tick/sec * 1/1000sec/msec)
#define XLLP_OST_TICKS_US 3 // 1usec in ticks (3.25x10^6tick/sec * 1/1000000sec/usec)
//static void XllpOstDelayTicks(volatile BULVERDE_OST_REG * pOstRegs, DWORD ticks)
static void XllpOstDelayTicks(DWORD ticks)
{
// volatile DWORD expireTime;
// volatile DWORD time=0;
/*
DWORD i,j;
for(j=0;j<ticks;j++)
{
for(i=0; i<20; i++ )
time += ticks;
}
pOstRegs->oscr0 = 0;
*/
/*
time = pOstRegs->oscr0;
expireTime = time + ticks;
//
// Check if we wrapped on the expireTime
// and delay first part until wrap
//
if (expireTime < time)
{
GSPIMSG(TICKCNTMSG,(L"%s, Timer is wrapped (expt, t)=(%xh, %xh)\n", TEXT(__FUNCTION__), expireTime, time));
while (time <= pOstRegs->oscr0);
GSPIMSG(TICKCNTMSG,(L"%s, timer is wrapped (leave)\n", TEXT(__FUNCTION__)));
}
while (pOstRegs->oscr0 <= expireTime);
//RETAILMSG(1,(L"oscr0 %x:%x,\n",expireTime,pOstRegs->oscr0));
*/
return;
}
void putcToSoc(PSSP_HARDWARE_CONTEXT pHC, UCHAR c)
{
while((pHC->pSSPRegs->SPSTA0 & 0x1)==0); // wait while busy
pHC->pSSPRegs->SPTDAT0 = c; // write left justified data
while((pHC->pSSPRegs->SPSTA0 & 0x1)==0); // wait while busy
return ;
}
//blacksu mod
void udelay(DWORD ms)
{
}
/*
void udelay(volatile BULVERDE_OST_REG *pOstRegs, DWORD ms)
{
DWORD ticks;
ticks = ms * XLLP_OST_TICKS_US * 3; // approx. 3 ticks per microsecond.
//XllpOstDelayTicks (pOstRegs, ticks);
XllpOstDelayTicks (ticks);
return;
}
*/
///////////////////////////////////////////////////////////////////////////////
/// Core functions of the SSP interface accessing
///
static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n)
{
GSPI_STATUS result = GSPI_SUCCESS;
DWORD dmaresult;
MYDMAPARAM *pDmaParam = &pHC->DMAParam[RWDMA_PARAM];
//DWORD TC;
// DMA mode, CLK enable, master mode, active high clock, format A, normal mode
pHC->pIntRegs->INTMSK&= ~(0x1<<18);//DMA1 service available
//pHC->pSSPRegs->SPCON0 = (0x10<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);
pHC->pSSPRegs->SPCON0 = (0x2<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);
//pHC->pDMARegs->DISRC1= (unsigned) (pHC->iodata);//Virtual address
pHC->pDMARegs->DISRC1= (unsigned) (pHC->phys_addr);//Phy address
pHC->pDMARegs->DISRCC1=(0<<1) | (0); //AHB(Memory), inc
pHC->pDMARegs->DIDST1=(unsigned)0x59000010;//SPI0 SPTDAT0 register(Physical Address)
pHC->pDMARegs->DIDSTC1=(1<<1) | (1);//APB(SPI), fixed
//Handshake Mode(31) , sync PCLK(30), TC intr(29), single TX(28), single service(27),
//request source SPI(26..24), H/W request(23), off-reload(22), data size:byte(21..20), transfer count
pHC->pDMARegs->DCON1=(1<<31) |(0<<30)|(1<<29)|(0<<28)|(0<<27)|(3<<24)|(1<<23)|(1<<22)|(0<<20)|(n);
/*
TC=n;
if(DMA_DATASIZE==2)
TC=(n+1)/2;
else if (DMA_DATASIZE==4)
TC=(n+3)/4;
pHC->pDMARegs->DCON1=(1<<31) |(0<<30)|(1<<29)|(0<<28)|(0<<27)|(3<<24)|(1<<23)|(1<<22)|(DMA_DATASIZE<<20)|(TC);
*/
#if (USE_DMAIRQ == 1)
ResetEvent(pDmaParam->dmaWaitObj);
#endif ///USE_DMAIRQ
pHC->pDMARegs->DMASKTRIG1=(0<<2)|(1<<1)|(0);//run, channel on, no s/w trigger
#if (USE_DMAIRQ == 1)
dmaresult = WaitForSingleObject(pDmaParam->dmaWaitObj, (MAX_WAITus/1000));
if (dmaresult == WAIT_TIMEOUT) {
GSPIMSG(1, (TEXT("setup_write_dma WaitForSingleObject timeout (%d)\n"), n));
result = GSPI_TIMEOUT;
goto funcFinal;
}
//GSPIMSG(1, (TEXT("good...\n")));
pHC->pDMARegs->DMASKTRIG1=(0<<2)|(0<<1)|(0);//run, channel off, no s/w trigger
#endif
funcFinal:
return result;
}
static GSPI_STATUS ssp_write_data_direct(DWORD hDC, PWORD data, WORD reg, WORD nword)
{
int result = GSPI_SUCCESS;
PSSP_HARDWARE_CONTEXT pHC;
int nbyte;
///crlo:length-fix ++
int fragnbyte, accnbyte;
BOOLEAN needToWriteReg = TRUE;
BOOLEAN isFrag = FALSE;
WORD temp;
BYTE temp1;
int i;
///crlo:length-fix --
#if (USE_DMA != 1)
int i;
PWORD dat;
#endif ///(USE_DMA != 1)
///GSPIMSG(1, (TEXT("w(%d)\n"), (nword*2)));
ENTERFUNC();
if (hDC == 0) {
result = GSPI_INVALIDARGS;
goto funcLeave;
}
pHC = (PSSP_HARDWARE_CONTEXT)hDC;
EnterCriticalSection(&pHC->SSPCrit);
///n is a unit of WORD. Convert it to unit of BYTE
nbyte = nword * 2;
reg |= 0x8000;
accnbyte = 0;
// poll mode, CLK enable, master mode, active high clock, format A, normal mode
pHC->pSSPRegs->SPCON0 = (0<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);
pHC->pSSPRegs->SPPIN0= ((0<<2) |(1<<1) |(0<<0));
pHC->pGPIORegs->GPGDAT &= ~(0x1 << 2); //Set _SS signal to low (Slave Select)
#if (USE_DMA == 1)
// DMAl mode, CLK enable, master mode, active high clock, format A, normal mode
pHC->pIntRegs->INTMSK&= ~(0x1<<18);//DMA1 service available
pHC->pSSPRegs->SPCON0 = (0x2<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);
#endif
//*dat=temp;
//RETAILMSG(1,(L"%02d READ Value=(0x%x)\r\n", i,*dat));
///crlo: Writing the data
while (1) {
if ((nbyte - accnbyte) > (PXA_SSP_IODATA_SIZE)) {
fragnbyte = PXA_SSP_IODATA_SIZE;
GSPIMSG(1, (TEXT("Fragment Tx Data (now, exp)=(%d, %d)\n"), accnbyte, nbyte));
isFrag = TRUE;
} else {
fragnbyte = nbyte - accnbyte;
}
memcpy(pHC->iodata,(BYTE*)®, 2);
memcpy(pHC->iodata+2, (BYTE*)data, fragnbyte);
for(i=0;i<nword+1;i++)
{
temp1=*(pHC->iodata+2*i);
*(pHC->iodata+2*i)=*(pHC->iodata+2*i+1);
*(pHC->iodata+2*i+1)=temp1;
}
//GSPIMSG(1, (TEXT("ssp_write_data_direct-----0=%02X 1=%02X 2=%02X 3=%02X)\n"), *(pHC->iodata), *(pHC->iodata+1),*(pHC->iodata+2),*(pHC->iodata+3)));
#if (USE_DMA == 1)
///DMA mode
result = setup_write_dma(pHC, fragnbyte+2);
if (result != GSPI_SUCCESS) {
GSPIMSG(1, (TEXT("Not successful after sending %d bytes.\n"), accnbyte));
break;
}
#else
///CPU mode
{
dat = (PWORD)pHC->iodata;
for (i=0 ; i<(fragnbyte/2) ; i++)
{
// pHC->pSSPRegs->base.ssdr = *dat;
temp=*dat;
while((pHC->pSSPRegs->SPSTA0 & 0x1)==0); // wait while busy
pHC->pSSPRegs->SPTDAT0 = (UCHAR)(temp >> 8); // write 1st Byte
// RETAILMSG(1,(L"ssp_write_data_direct(): Reg 1st Byte=(0x%x)\n", (UCHAR)(temp >> 8)));
while((pHC->pSSPRegs->SPSTA0 & 0x1)==0); // wait while busy
pHC->pSSPRegs->SPTDAT0 = (UCHAR)(temp & 0x00ff); // write 2nd Byte
// RETAILMSG(1,(L"ssp_write_data_direct(): Reg 1st Byte=(0x%x)\n", (UCHAR)(temp & 0x00ff)));
while((pHC->pSSPRegs->SPSTA0 & 0x1)==0); // wait while busy
dat ++;
}
}
#endif ///USE_DMA
data += (fragnbyte/2); ///type of Data is WORD
accnbyte += fragnbyte;
if (accnbyte == nbyte) {
if (isFrag == TRUE) {
GSPIMSG(1, (TEXT("Sending %d bytes complete\n"), accnbyte));
}
break;
} else if (accnbyte > nbyte) {
GSPIMSG(1, (TEXT("Invalid fragment, (exp, acc)=(%d, %d).\n"), nbyte, accnbyte));
break;
}
}
// poll mode, CLK enable, master mode, active high clock, format A, normal mode
pHC->pSSPRegs->SPCON0 = (0<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);
pHC->pSSPRegs->SPPIN0= ((0<<2) |(1<<1) |(0<<0));
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