em78p259.h

使用低成本单片机义隆EM78P259的有刷电机控制器程序

/********************************************************
 *	Header file for the Elan			     			*
 *	EM78P259/260 chip					     				*	
 *	Tilte:       EM78P259 include file                 * 
 * 	Description: The Definition of EM78P259 Registers  *
 * 	Company:     HONGSUO LTD.
 * 	Author:      JIANGKE			     			*
 * 	Date:        7/03/2006                             *
 *	Version:                                        *
 ********************************************************/
 
static unsigned int TCC		@0x01;
static unsigned int PC      @0x02;
static unsigned int STATUS  @0x03;
static unsigned int RSR		@0x04;
static unsigned int PORT5   @0x05;
static unsigned int PORT6   @0x06;
static unsigned int PORT7   @0x07;
static unsigned int ADCISR	@0x08;//AD input select register
static unsigned int ADCON	@0x09;//AD control register
static unsigned int ADOC	@0x0A;//AD offset calibration register
static unsigned int ADDATA		@0x0B;//AD data buffer AD11-AD4
static unsigned int ADDATAH		@0x0C;//AD data buffer HIGH
static unsigned int ADDATAL		@0x0D;//AD data buffer LOW
static unsigned int IRCR		@0x0E;//IR and WAKE-UP Control Register
static unsigned int ISR			@0x0F;//interrupt status register

static io unsigned int CONT @0x01:iopage 0;
static io unsigned int P5CR @0x05:iopage 0;
static io unsigned int P6CR @0x06:iopage 0;
static io unsigned int P7CR @0x07:iopage 0;
static io unsigned int IOC80 @0x08:iopage 0;
static io unsigned int IOC90	@0x09:iopage 0;
static io unsigned int IOCA0	@0x0a:iopage 0;
static io unsigned int IOCB0	@0x0b:iopage 0;
static io unsigned int IOCC0	@0x0c:iopage 0;//128 byte RAM address
//static io unsigned int IRCR 	@0x0A:iopage 0;//128 byte RAM buffer
//static io unsigned int PDCR 	@0x0B:iopage 0;//Counter1 preset
//static io unsigned int OCR 	@0x0C:iopage 0;//Counter2 preset
static io unsigned int PHCR 	@0x0D:iopage 0;
static io unsigned int IOCE0	@0x0e:iopage 0;
static io unsigned int IOCF0	@0x0F:iopage 0;//high-pulse width timer preset
/*static io unsigned int WDTCR 	@0x0E:iopage 0;//low-pulse width timer preset
static io unsigned int IMR 		@0x0F:iopage 0;//interrupt mask register*/

//static io unsigned int TCCAC		@0x06:iopage 1;
static io unsigned int TCCBL		@0x06:iopage 1;//Wake up & P5.7 sink current
static io unsigned int TCCBH 	@0x07:iopage 1;//TCC & INT0 control register
static io unsigned int TCCCC 	@0x08:iopage 1;//WDT control register
static io unsigned int LTR 	@0x09:iopage 1;//counter1,2 control
static io unsigned int HTR 	@0x0A:iopage 1;//high/low pulse width timer control
static io unsigned int ICOB1 	@0x0B:iopage 1;//port6 pull-high control
static io unsigned int TCCPC 	@0x0C:iopage 1;//port6 open-drain control


/*	STATUS bits	*/
static bit RST @0x03@7:rpage 0;
static bit IOCS @0x03@6:rpage 0;
static bit PS0 @0x03@5:rpage 0;	//page select bits
static bit T   @0x03@4:rpage 0;
static bit P   @0x03@3:rpage 0;
static bit Z   @0x03@2:rpage 0;
static bit DC  @0x03@1:rpage 0;
static bit C   @0x03@0:rpage 0;

/*	R4 bits	*/
//static bit R57 @0x05@7:rpage 0;
static bit BANKSEL @0x05@6:rpage 0;
//static bit R55 @0x05@5:rpage 0;
//static bit R54 @0x05@4:rpage 0;
//static bit IOCPAGE @0x05@0:rpage 0;//change IOC8 ~ IOCF to another page, 0/1 => page0 / page1
/*	R5 bits	*/
static bit R57	@0x05@7:rpage 0;
static bit R56	@0x05@6:rpage 0;
static bit R55  @0x05@5:rpage 0;
static bit R54	@0x05@4:rpage 0;
static bit R53  @0x05@3:rpage 0;
static bit R52	@0x05@2:rpage 0;
static bit R51	@0x05@1:rpage 0;
static bit R50	@0x05@0:rpage 0;
/*	R6 bits	*/
static bit R67	@0x06@7:rpage 0;
static bit R66	@0x06@6:rpage 0;
static bit R65  @0x06@5:rpage 0;
static bit R64	@0x06@4:rpage 0;
static bit R63  @0x06@3:rpage 0;
static bit R62	@0x06@2:rpage 0;
static bit R61	@0x06@1:rpage 0;
static bit R60	@0x06@0:rpage 0;
/*R7 bits8*/
static bit C3	@0x07@7:rpage 0;
static bit C2	@0x07@6:rpage 0;
static bit C1	@0x07@5:rpage 0;
static bit C0	@0x07@4:rpage 0;
static bit RCM1	@0x07@3:rpage 0;
static bit RCM0	@0x07@2:rpage 0;
//static bit R71	@0x07@1:rpage 0;
static bit R70	@0x07@0:rpage 0;
/*	R8 bits	*/
//static bit R87	@0x08@7:rpage 0;
//static bit R86	@0x08@6:rpage 0;
//static bit R85	@0x08@5:rpage 0;
//static bit R84	@0x08@4:rpage 0;
static bit ADE3	@0x08@3:rpage 0;
static bit ADE2	@0x08@2:rpage 0;
static bit ADE1	@0x08@1:rpage 0;
static bit ADE0	@0x08@0:rpage 0;

/* ADC control register	*/
static bit VREFS 	@0x09@7:rpage 0;
static bit CKR1 		@0x09@6:rpage 0;
static bit CKR0 		@0x09@5:rpage 0;
//ADC CLOCK select
//CKR1 CKR0 ADC CLOCK
// 0   0    1/16 Fsco
// 0   1    1/4 Fsco
// 1   0    1/64 Fsco
// 1   1    Internal RC
static bit ADRUN	@0x09@4:rpage 0;
static bit ADPD 	@0x09@2:rpage 0;

static bit ADIS1 	@0x09@1:rpage 0;
static bit ADIS0	@0x09@0:rpage 0;

//AD CHANNEL SLECT
// 0   0     P50
// 0   1     P51
// 1   0     P52
// 1   1     P53

/*ADOC BITS*/
static bit CALI	@0x0A@7:rpage 0;
static bit SIGN 	@0x0A@6:rpage 0;
static bit VOF2		@0x0A@5:rpage 0;
static bit VOF1 	@0x0A@4:rpage 0;
static bit VOF0 	@0x0A@3:rpage 0;

/*	RE BITS	*/
static bit ADIF 	@0x0e@5:rpage 0;
static bit CMPIF 	@0x0e@4:rpage 0;
static bit ADWE 	@0x0e@3:rpage 0;
static bit CMPWE 		@0x0e@2:rpage 0;
static bit ICWE		@0x0e@1:rpage 0;
/*
Bit 6~4 (CLK2~0): 
main clock select bit for PLL mode (code option select)
CLK2 CLK1 CLK0 Main clock
  0   0    0    32.768K*130=4.26 MHz
  0   0    1    32.768K*65=2.13 MHz
  0   1    0    2.13MHz/2
  0   1    1    2.13MHz/4
  1   --   --   32.768K*244=8 MHz
Bit 3 (IDLE): 
idle mode enable bit. This bit will decide the intended mode of the SLEP instruction.
IDLE=”0”+SLEP instruction => sleep mode
IDLE=”1”+SLEP instruction => idle mode
Bit 2,1 (BF1, 0): 
LCD booster frequency select bit
BF1 BF0 Booster frequency
 0   0     Fs
 0   1     Fs/4
 1   0     Fs/8
 1   1     Fs/16
Bit 0 (CPUS): 
CPU oscillator source select, 0/1=> sub-oscillator (Fs)/ main oscillator (Fm)
When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped.
*/

/*	IR Control and PORT5 Function Pins Set Register	*/
static bit IRE	@0x0e@7:rpage 0;
static bit HF	@0x0e@6:rpage 0;
static bit LGP	@0x0e@5:rpage 0;
//not used
static bit IROUTE	@0x0e@3:rpage 0;
static bit TCCE		@0x0e@2:rpage 0;
static bit EINT1	@0x0e@1:rpage 0;
static bit EINT0	@0x0e@0:rpage 0;
/*
Bit 7 	Bit 6 	Bit 5 	Bit 4 	Bit 3 	Bit 2 	Bit 1 	Bit 0
 IRE 	  HF     LGP      --    IROUTE   TCCE   EINT1   EINT0
 
Bit 7 (IRE): Infrared Remote Enable bit
0: Disable IRE. Disable H/W Modulator Function. IROUT pin fixed to high level
1: Enable IRE. Enable H/W Modulator Function. Pin 6.7 defined as IROUT.
Bit 6 (HF): High frequency.
0: For PWM application, IROUT waveform is created according to high-pulse and low-pulse
width time as determined by the high pulse and low pulse width timers respectively.
1: For IR application mode, the low time sections of the generated pulse is modulated with
the frequency Fcarrier,
Bit 5 (LGP): long pulse.
0: the high-pulse timer register and low-pulse width timer is valid.
1: The high-pulse width timer register is ignored. So the IROUT waveform is dependent on
low-pulse width timer register only
Bit 4: Not used
Bit 3 (IROUTE): control bit is used to define the function of P5.7 (IROUT) pin.
0: P5.7, bi-directional I/O pin.
1: IROUT, in this case, the I/O control bit of P5.7 (bit 7 of IOC5) must be set to “0”
Bit 2 (TCCE): control bit is used to define the function of P5.6 (TCC) pin.
0: P5.6, bi-directional I/O pin.
1: TCC, external input pin of TCC. In this case, the I/O control bit of P5.6 (bit 6 of IOC5)
must be set to “1”
Bit 1 (EINT1): control bit is used to define the function of P5.5 (INT1) pin.
0: P5.5, bi-directional I/O pin.
1: INT1, external interrupt pin. In this case, the I/O control bit of P5.5 (bit 5 of IOC5) must be
set to “1”
Bit 0 (EINT0): control bit is used to define the function of P5.4 (INT0) pin.
0: P5.4, bi-directional I/O pin.
1: INT0, external interrupt pin. In this case, the I/O control bit of P5.4 (bit 4 of IOC5) must be
set to “1”
*/

/*	Interrupt Status Register	*/
static bit ICIF		@0x0f@7:rpage 0;
static bit LPWTF 	@0x0f@6:rpage 0;
static bit HPWTF 	@0x0f@5:rpage 0;
static bit CNT2F	@0x0f@4:rpage 0;
static bit CNT1F 	@0x0f@3:rpage 0;
static bit INT1F 	@0x0f@2:rpage 0;
static bit INT0F 	@0x0f@1:rpage 0;
static bit TCIF		@0x0f@0:rpage 0;
/*
Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when PORT6, PORT8 input
changes.
Bit 6 (LPWTF): interrupt flag of internal low-pulse width timer underflow.
Bit 5 (HPWTF): interrupt flag of internal high-pulse width timer underflow.
Bit 4 (CNT2): interrupt flag of internal counter 2 under-flow.
Bit 3 (CNT1): interrupt flag of internal counter 1 underflow.
Bit 2 (INT1F): external INT1 pin interrupt flag.
Bit 1 (INT0F): external INT0 pin interrupt flag.
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
*/