📄 add_8tr1.mdl
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Points [55, 0; 0, 85]
DstBlock "Matrix\nConcatenation1"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 6
Points [110, 0; 0, 80]
DstBlock "Matrix\nConcatenation1"
DstPort 2
}
Line {
SrcBlock "Demux1"
SrcPort 7
Points [35, 0; 0, 75]
DstBlock "Matrix\nConcatenation1"
DstPort 3
}
Line {
SrcBlock "Demux1"
SrcPort 8
Points [10, 0; 0, 70]
DstBlock "Matrix\nConcatenation1"
DstPort 4
}
}
}
Block {
BlockType SubSystem
Name "Subsystem2"
Ports [1, 8]
Position [340, 42, 480, 268]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Subsystem2"
Location [22, 82, 1018, 692]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [15, 208, 45, 222]
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "DSP\nConstant1"
Ports [0, 1]
Position [535, 99, 570, 131]
SourceBlock "dspsrcs4/DSP\nConstant"
SourceType "DSP Constant"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Value "[0 0 0 0;0 0 0 0;0 0 0 0;0 0 0 0]"
SampleMode "Discrete"
discreteOutput "Sample-based"
continuousOutput "Sample-based"
sampTime "12e-6"
framePeriod "2"
additionalParams off
allowOverrides on
dataType "Inherit from 'Constant value'"
isSigned on
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
InterpretAs1D "-inf"
Ts "-inf"
FramebasedOutput "-inf"
}
Block {
BlockType Reference
Name "DSP\nConstant2"
Ports [0, 1]
Position [450, 314, 485, 346]
SourceBlock "dspsrcs4/DSP\nConstant"
SourceType "DSP Constant"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Value "[0 0 0 0;0 0 0 0;0 0 0 0;0 0 0 0]"
SampleMode "Discrete"
discreteOutput "Sample-based"
continuousOutput "Sample-based"
sampTime "12e-6"
framePeriod "2"
additionalParams off
allowOverrides on
dataType "Inherit from 'Constant value'"
isSigned on
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
InterpretAs1D "-inf"
Ts "-inf"
FramebasedOutput "-inf"
}
Block {
BlockType Reference
Name "Frame Status\nConversion"
Ports [1, 1]
Position [855, 262, 890, 298]
SourceBlock "dspobslib/Frame Status\nConversion"
SourceType "Frame Status Conversion"
ShowPortLabels off
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
growRefPort off
outframe "Frame-based"
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn1"
Position [125, 70, 185, 100]
MATLABFcn "add1(u)"
OutputDimensions "[4,4]"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn2"
Position [130, 245, 190, 275]
MATLABFcn "minu(u)"
OutputDimensions "[4,4]"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn3"
Position [125, 135, 185, 165]
MATLABFcn "xishu1(u)"
OutputDimensions "1"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn4"
Position [115, 300, 175, 330]
MATLABFcn "xishu2(u)"
OutputDimensions "1"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation1"
Ports [2, 1]
Position [600, 55, 640, 135]
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation2"
Ports [2, 1]
Position [520, 315, 560, 395]
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation3"
Ports [2, 1]
Position [670, 240, 710, 320]
Mode "Vertical matrix concatenation"
}
Block {
BlockType Product
Name "Matrix Multiply1"
Ports [2, 1]
Position [295, 236, 350, 274]
Multiplication "Matrix(*)"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Matrix Multiply7"
Ports [2, 1]
Position [355, 107, 405, 138]
Multiplication "Matrix(*)"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Multiport\nSelector"
Tag "S/P"
Description "S/P"
Ports [1, 8]
Position [915, 77, 945, 463]
SourceBlock "dspindex/Multiport\nSelector"
SourceType "Multiport Selector"
rowsOrCols "Rows"
idxCellArray "{1,2,3,4,5,6,7,8}"
idxErrMode "Clip Index"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [475, 70, 520, 105]
InputSameDT off
RndMeth "Floor"
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [415, 201, 460, 234]
InputSameDT off
RndMeth "Floor"
}
Block {
BlockType Reference
Name "Reshape1"
Ports [1, 1]
Position [1030, 283, 1060, 307]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape2"
Ports [1, 1]
Position [1025, 83, 1055, 107]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape3"
Ports [1, 1]
Position [1030, 133, 1060, 157]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape4"
Ports [1, 1]
Position [1025, 183, 1055, 207]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape5"
Ports [1, 1]
Position [1030, 233, 1060, 257]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape6"
Ports [1, 1]
Position [1030, 333, 1060, 357]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape7"
Ports [1, 1]
Position [1035, 383, 1065, 407]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType Reference
Name "Reshape8"
Ports [1, 1]
Position [1035, 433, 1065, 457]
SourceBlock "simulink/Math\nOperations/Reshape"
SourceType "Reshape"
OutputDimensionality "Column vector"
OutputDimensions "[2,2]"
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [845, 390, 905, 420]
VariableName "simout"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace2"
Position [755, 30, 815, 60]
VariableName "simout2"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType Reference
Name "Transpose1"
Ports [1, 1]
Position [50, 214, 75, 236]
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Hermitian off
overflowFlag off
}
Block {
BlockType UnitDelay
Name "Unit Delay1"
Position [355, 25, 390, 65]
Orientation "left"
X0 "[1 0 0 0;0 1 0 0;0 0 1 0;0 0 0 1]"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay2"
Position [295, 155, 330, 195]
Orientation "left"
X0 "[1 0 0 0;0 1 0 0;0 0 1 0;0 0 0 1]"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay3"
Position [195, 100, 235, 135]
Orientation "up"
X0 "1"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay4"
Position [195, 295, 230, 335]
X0 "1"
SampleTime "-1"
}
Block {
BlockType Outport
Name "antenna1"
Position [1165, 83, 1195, 97]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna2"
Position [1175, 133, 1205, 147]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna3"
Position [1185, 184, 1215, 196]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna4"
Position [1180, 233, 1210, 247]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna5"
Position [1180, 293, 1210, 307]
Port "5"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna6"
Position [1175, 338, 1205, 352]
Port "6"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna7"
Position [1180, 388, 1210, 402]
Port "7"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "antenna8"
Position [1180, 438, 1210, 452]
Port "8"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Unit Delay1"
SrcPort 1
Points [-45, 0; 0, 70]
DstBlock "Matrix Multiply7"
DstPort 1
}
Line {
SrcBlock "Reshape3"
SrcPort 1
Points [95, 0]
DstBlock "antenna2"
DstPort 1
}
Line {
SrcBlock "Reshape4"
SrcPort 1
Points [0, -5]
DstBlock "antenna3"
DstPort 1
}
Line {
SrcBlock "Reshape5"
SrcPort 1
Points [0, -5]
DstBlock "antenna4"
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