📄 add_8tr1.mdl
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OutputDimensions "[2,1]"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn2"
Position [875, 425, 935, 455]
MATLABFcn "compute(u)"
OutputDimensions "[1,2]"
OutputSignalType "real"
Output1D off
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn3"
Position [640, 270, 700, 300]
MATLABFcn "demodulation3(u)"
OutputDimensions "[2,1]"
OutputSignalType "complex"
Output1D off
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation1"
Ports [4, 1]
Position [370, 237, 405, 338]
NumInputs "4"
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation2"
Ports [4, 1]
Position [375, 77, 400, 188]
NumInputs "4"
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation3"
Ports [3, 1]
Position [795, 406, 830, 474]
NumInputs "3"
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation4"
Ports [2, 1]
Position [485, 119, 520, 186]
Mode "Vertical matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation5"
Ports [2, 1]
Position [490, 284, 525, 351]
Mode "Vertical matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation6"
Ports [3, 1]
Position [570, 176, 605, 244]
NumInputs "3"
Mode "Vertical matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation7"
Ports [2, 1]
Position [945, 180, 985, 235]
Mode "Vertical matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation8"
Ports [3, 1]
Position [725, 176, 760, 244]
NumInputs "3"
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Concatenate
Name "Matrix\nConcatenation9"
Ports [3, 1]
Position [665, 532, 700, 618]
NumInputs "3"
Mode "Horizontal matrix concatenation"
}
Block {
BlockType Reference
Name "Multiport\nSelector"
Tag "S/P"
Description "S/P"
Ports [1, 2]
Position [775, 166, 815, 259]
SourceBlock "dspindex/Multiport\nSelector"
SourceType "Multiport Selector"
rowsOrCols "Rows"
idxCellArray "{1,2}"
idxErrMode "Clip Index"
}
Block {
BlockType Reference
Name "QPSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [885, 31, 925, 69]
LinkData {
BlockName "M-PSK\nDemodulator\nBaseband"
DialogParameters {
OutType "Bit"
Dec "Binary"
}
}
SourceBlock "commdigbbndpm2/QPSK\nDemodulator\nBaseband"
SourceType "QPSK Demodulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
OutType "Bit"
Dec "Binary"
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "QPSK\nDemodulator\nBaseband1"
Ports [1, 1]
Position [885, 310, 920, 350]
SourceBlock "commdigbbndpm2/QPSK\nDemodulator\nBaseband"
SourceType "QPSK Demodulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
OutType "Bit"
Dec "Binary"
Ph "pi/4"
numSamp "1"
}
Block {
BlockType Reference
Name "Transpose1"
Ports [1, 1]
Position [772, 75, 818, 105]
Orientation "up"
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Hermitian off
overflowFlag off
}
Block {
BlockType Reference
Name "Transpose2"
Ports [1, 1]
Position [767, 290, 813, 320]
Orientation "down"
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Hermitian off
overflowFlag off
}
Block {
BlockType UnitDelay
Name "Unit Delay1"
Position [430, 325, 465, 365]
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay2"
Position [430, 150, 465, 190]
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay4"
Position [845, 497, 885, 533]
Orientation "left"
X0 "[1 1]"
SampleTime "-1"
}
Block {
BlockType Outport
Name "Out1"
Position [1040, 203, 1070, 217]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Frame Status\nConversion3"
SrcPort 1
Points [20, 0]
DstBlock "Demux1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Frame Status\nConversion3"
DstPort 1
}
Line {
SrcBlock "Unit Delay2"
SrcPort 1
DstBlock "Matrix\nConcatenation4"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation1"
SrcPort 1
Points [0, 10; 5, 0]
Branch {
DstBlock "Matrix\nConcatenation5"
DstPort 1
}
Branch {
DstBlock "Unit Delay1"
DstPort 1
}
}
Line {
SrcBlock "Unit Delay1"
SrcPort 1
Points [0, -10]
DstBlock "Matrix\nConcatenation5"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation4"
SrcPort 1
Points [15, 0; 0, 35]
DstBlock "Matrix\nConcatenation6"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation5"
SrcPort 1
Points [10, 0; 0, -110]
DstBlock "Matrix\nConcatenation6"
DstPort 2
}
Line {
SrcBlock "QPSK\nDemodulator\nBaseband"
SrcPort 1
DstBlock "Matrix\nConcatenation7"
DstPort 1
}
Line {
SrcBlock "QPSK\nDemodulator\nBaseband1"
SrcPort 1
Points [5, 0]
DstBlock "Matrix\nConcatenation7"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation7"
SrcPort 1
DstBlock "Frame Status\nConversion4"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation3"
SrcPort 1
DstBlock "MATLAB Fcn2"
DstPort 1
}
Line {
SrcBlock "Frame Status\nConversion4"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation8"
SrcPort 1
Points [0, 5]
DstBlock "Multiport\nSelector"
DstPort 1
}
Line {
SrcBlock "Multiport\nSelector"
SrcPort 1
Points [15, 0; 0, -70]
DstBlock "Transpose1"
DstPort 1
}
Line {
SrcBlock "Multiport\nSelector"
SrcPort 2
Points [30, 0; 0, 40]
DstBlock "Transpose2"
DstPort 1
}
Line {
SrcBlock "Transpose2"
SrcPort 1
Points [0, 5]
DstBlock "Frame Status\nConversion2"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation2"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Matrix\nConcatenation4"
DstPort 1
}
Branch {
DstBlock "Unit Delay2"
DstPort 1
}
}
Line {
SrcBlock "Matrix\nConcatenation6"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "MATLAB Fcn1"
DstPort 1
}
Branch {
Points [0, 75]
DstBlock "MATLAB Fcn3"
DstPort 1
}
Branch {
Points [0, -75]
DstBlock "MATLAB Fcn"
DstPort 1
}
}
Line {
SrcBlock "MATLAB Fcn"
SrcPort 1
Points [5, 0; 0, 5]
Branch {
Points [0, 50]
DstBlock "Matrix\nConcatenation8"
DstPort 1
}
Branch {
Points [45, 0; 0, 280]
DstBlock "Matrix\nConcatenation3"
DstPort 1
}
}
Line {
SrcBlock "MATLAB Fcn1"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Matrix\nConcatenation8"
DstPort 2
}
Branch {
Points [5, 0; 0, 170; -90, 0; 0, 60]
DstBlock "Matrix\nConcatenation3"
DstPort 2
}
}
Line {
SrcBlock "MATLAB Fcn3"
SrcPort 1
Points [0, -35]
Branch {
Points [0, -20]
DstBlock "Matrix\nConcatenation8"
DstPort 3
}
Branch {
Points [-35, 0; 0, 215; 80, 0; 0, -5]
DstBlock "Matrix\nConcatenation3"
DstPort 3
}
}
Line {
SrcBlock "MATLAB Fcn2"
SrcPort 1
Points [20, 0; 0, 75]
DstBlock "Unit Delay4"
DstPort 1
}
Line {
SrcBlock "DSP\nConstant1"
SrcPort 1
DstBlock "Matrix\nConcatenation9"
DstPort 2
}
Line {
SrcBlock "DSP\nConstant2"
SrcPort 1
DstBlock "Matrix\nConcatenation9"
DstPort 3
}
Line {
SrcBlock "Matrix\nConcatenation9"
SrcPort 1
Points "[30, 0; 0, 65; -225, 0; 0, -270; 50, 0; 0, "
"-140]"
DstBlock "Matrix\nConcatenation6"
DstPort 3
}
Line {
SrcBlock "Frame Status\nConversion2"
SrcPort 1
DstBlock "QPSK\nDemodulator\nBaseband1"
DstPort 1
}
Line {
SrcBlock "Frame Status\nConversion1"
SrcPort 1
DstBlock "QPSK\nDemodulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "Transpose1"
SrcPort 1
Points [0, -20]
DstBlock "Frame Status\nConversion1"
DstPort 1
}
Line {
SrcBlock "Unit Delay4"
SrcPort 1
Points [-225, 0; 0, 30]
DstBlock "Matrix\nConcatenation9"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 1
Points [160, 0; 0, 50]
DstBlock "Matrix\nConcatenation2"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 2
Points [130, 0; 0, 45]
DstBlock "Matrix\nConcatenation2"
DstPort 2
}
Line {
SrcBlock "Demux1"
SrcPort 3
Points [90, 0; 0, 40]
DstBlock "Matrix\nConcatenation2"
DstPort 3
}
Line {
SrcBlock "Demux1"
SrcPort 4
Points [65, 0; 0, 35]
DstBlock "Matrix\nConcatenation2"
DstPort 4
}
Line {
SrcBlock "Demux1"
SrcPort 5
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