📄 add_4tr1.mdl
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Name "Sum1"
Ports [2, 1]
Position [290, 170, 320, 200]
ShowName off
IconShape "round"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [230, 330, 260, 360]
ShowName off
IconShape "round"
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum3"
Ports [2, 1]
Position [310, 260, 340, 290]
ShowName off
IconShape "round"
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum4"
Ports [2, 1]
Position [250, 510, 280, 540]
ShowName off
IconShape "round"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum5"
Ports [2, 1]
Position [280, 575, 310, 605]
ShowName off
IconShape "round"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum6"
Ports [2, 1]
Position [220, 735, 250, 765]
ShowName off
IconShape "round"
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum7"
Ports [2, 1]
Position [300, 665, 330, 695]
ShowName off
IconShape "round"
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Reference
Name "Transpose1"
Ports [1, 1]
Position [772, 75, 818, 105]
Orientation "up"
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
Hermitian off
}
Block {
BlockType Reference
Name "Transpose2"
Ports [1, 1]
Position [767, 290, 813, 320]
Orientation "down"
SourceBlock "dspmtrx3/Transpose"
SourceType "Transpose"
Hermitian off
}
Block {
BlockType UnitDelay
Name "Unit Delay1"
Position [430, 325, 465, 365]
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay2"
Position [430, 150, 465, 190]
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay3"
Position [732, 360, 768, 400]
Orientation "down"
X0 "[1;0]"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay4"
Position [607, 395, 643, 435]
Orientation "down"
X0 "[0;1]"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay5"
Position [420, 730, 455, 770]
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "Unit Delay6"
Position [420, 555, 455, 595]
SampleTime "-1"
}
Block {
BlockType Outport
Name "Out1"
Position [1040, 203, 1070, 217]
}
Line {
SrcBlock "Frame Status\nConversion3"
SrcPort 1
Points [20, 0]
DstBlock "Demux1"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 1
Points [0, 40; 60, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Points [0, -40; 90, 0]
DstBlock "Sum3"
DstPort 1
}
}
Line {
SrcBlock "Demux1"
SrcPort 3
Points [0, 0; 55, 0]
Branch {
Points [45, 0]
DstBlock "Sum"
DstPort 2
}
Branch {
Points [0, 125]
DstBlock "Sum3"
DstPort 2
}
}
Line {
SrcBlock "Demux1"
SrcPort 2
Points [0, 40; 10, 0]
Branch {
Points [0, 160]
DstBlock "Sum2"
DstPort 1
}
Branch {
DstBlock "Sum1"
DstPort 1
}
}
Line {
SrcBlock "Demux1"
SrcPort 4
Points [0, 0; 30, 0]
Branch {
Points [100, 0]
DstBlock "Sum1"
DstPort 2
}
Branch {
Points [0, 130]
DstBlock "Sum2"
DstPort 2
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Matrix\nConcatenation2"
DstPort 1
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [10, 0; 0, -40]
DstBlock "Matrix\nConcatenation2"
DstPort 2
}
Line {
SrcBlock "Sum3"
SrcPort 1
Points [0, 25]
DstBlock "Matrix\nConcatenation1"
DstPort 1
}
Line {
SrcBlock "Sum2"
SrcPort 1
Points [40, 0; 0, -20]
DstBlock "Matrix\nConcatenation1"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Frame Status\nConversion3"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation2"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
Points [55, 0]
DstBlock "Matrix\nConcatenation4"
DstPort 1
}
Branch {
DstBlock "Unit Delay2"
DstPort 1
}
}
Line {
SrcBlock "Unit Delay2"
SrcPort 1
DstBlock "Matrix\nConcatenation4"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation1"
SrcPort 1
Points [0, -15; 5, 0]
Branch {
DstBlock "Matrix\nConcatenation5"
DstPort 1
}
Branch {
DstBlock "Unit Delay1"
DstPort 1
}
}
Line {
SrcBlock "Unit Delay1"
SrcPort 1
Points [0, -10]
DstBlock "Matrix\nConcatenation5"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation4"
SrcPort 1
Points [15, 0; 0, 45]
DstBlock "Matrix\nConcatenation6"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation5"
SrcPort 1
Points [10, 0; 0, -105]
DstBlock "Matrix\nConcatenation6"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation6"
SrcPort 1
Points [5, 0; 0, -30]
Branch {
DstBlock "MATLAB Fcn"
DstPort 1
}
Branch {
DstBlock "MATLAB Fcn1"
DstPort 1
}
}
Line {
SrcBlock "QPSK\nDemodulator\nBaseband"
SrcPort 1
DstBlock "Matrix\nConcatenation7"
DstPort 1
}
Line {
SrcBlock "QPSK\nDemodulator\nBaseband1"
SrcPort 1
Points [5, 0]
DstBlock "Matrix\nConcatenation7"
DstPort 2
}
Line {
SrcBlock "Frame Status\nConversion1"
SrcPort 1
DstBlock "QPSK\nDemodulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "Frame Status\nConversion2"
SrcPort 1
DstBlock "QPSK\nDemodulator\nBaseband1"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation7"
SrcPort 1
DstBlock "Frame Status\nConversion4"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation3"
SrcPort 1
DstBlock "MATLAB Fcn2"
DstPort 1
}
Line {
SrcBlock "Unit Delay3"
SrcPort 1
Points [0, 15]
DstBlock "Matrix\nConcatenation3"
DstPort 1
}
Line {
SrcBlock "Unit Delay4"
SrcPort 1
Points [0, 15]
DstBlock "Matrix\nConcatenation3"
DstPort 2
}
Line {
SrcBlock "MATLAB Fcn"
SrcPort 1
Points [10, 0; 0, 30]
Branch {
DstBlock "Matrix\nConcatenation8"
DstPort 1
}
Branch {
Points [-35, 0; 0, 105; 75, 0]
DstBlock "Unit Delay3"
DstPort 1
}
}
Line {
SrcBlock "MATLAB Fcn1"
SrcPort 1
Points [10, 0; 0, -5]
Branch {
DstBlock "Matrix\nConcatenation8"
DstPort 2
}
Branch {
Points [0, 40; -85, 0]
DstBlock "Unit Delay4"
DstPort 1
}
}
Line {
SrcBlock "Frame Status\nConversion4"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenation8"
SrcPort 1
DstBlock "Multiport\nSelector"
DstPort 1
}
Line {
SrcBlock "Multiport\nSelector"
SrcPort 1
Points [15, 0; 0, -70]
DstBlock "Transpose1"
DstPort 1
}
Line {
SrcBlock "Transpose1"
SrcPort 1
Points [0, -15]
DstBlock "Frame Status\nConversion1"
DstPort 1
}
Line {
SrcBlock "Multiport\nSelector"
SrcPort 2
Points [30, 0; 0, 40]
DstBlock "Transpose2"
DstPort 1
}
Line {
SrcBlock "Transpose2"
SrcPort 1
Points [0, 5]
DstBlock "Frame Status\nConversion2"
DstPort 1
}
Line {
SrcBlock "Frame Status\nConversion5"
SrcPort 1
Points [15, 0]
DstBlock "Demux2"
DstPort 1
}
Line {
SrcBlock "Demux2"
SrcPort 1
Points [0, 40; 60, 0]
Branch {
DstBlock "Sum4"
DstPort 1
}
Branch {
Points [0, -40; 90, 0]
DstBlock "Sum7"
DstPort 1
}
}
Line {
SrcBlock "Demux2"
SrcPort 3
Points [0, 0; 55, 0]
Branch {
Points [45, 0]
DstBlock "Sum4"
DstPort 2
}
Branch {
Points [0, 125]
DstBlock "Sum7"
DstPort 2
}
}
Line {
SrcBlock "Demux2"
SrcPort 2
Points [0, 40; 10, 0]
Branch {
Points [0, 160]
DstBlock "Sum6"
DstPort 1
}
Branch {
DstBlock "Sum5"
DstPort 1
}
}
Line {
SrcBlock "Demux2"
SrcPort 4
Points [0, 0; 30, 0]
Branch {
Points [100, 0]
DstBlock "Sum5"
DstPort 2
}
Branch {
Points [0, 130]
DstBlock "Sum6"
DstPort 2
}
}
Line {
SrcBlock "Sum4"
SrcPort 1
DstBlock "Matrix\nConcatenation10"
DstPort 1
}
Line {
SrcBlock "Sum5"
SrcPort 1
Points [10, 0; 0, -40]
DstBlock "Matrix\nConcatenation10"
DstPort 2
}
Line {
SrcBlock "Sum7"
SrcPort 1
Points [0, 25]
DstBlock "Matrix\nConcatenation9"
DstPort 1
}
Line {
SrcBlock "Sum6"
SrcPort 1
Points [40, 0; 0, -20]
DstBlock "Matrix\nConcatenation9"
DstPort 2
}
Line {
SrcBlock "Matrix\nConcatenation10"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
Points [55, 0]
DstBlock "Matrix\nConcatenation11"
DstPort 1
}
Branch {
DstBlock "Unit Delay6"
DstPort 1
}
}
Line {
SrcBlock "Unit Delay6"
SrcPort 1
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