dm9ks_s3c2440_20070201.c

dm9000驱动目前在linux2.4.18上测试能正常使用

/*

  dm9ks.c: Version 2.03 2005/10/17 
  
        A Davicom DM9000A/DM9010 ISA NIC fast Ethernet driver for Linux.

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.


  (C)Copyright 1997-2005 DAVICOM Semiconductor,Inc. All Rights Reserved.

	
V1.00	10/13/2004	Add new function Early transmit & IP/TCP/UDP Checksum
			offload enable & flow control is default
V1.1	12/29/2004	Add Two packet mode & modify RX function
V1.2	01/14/2005	Add Early transmit mode 
V1.3	03/02/2005	Support kernel 2.6
v1.33   06/08/2005	#define DM9KS_MDRAL		0xf4
			#define DM9KS_MDRAH		0xf5
			
V2.00 Spenser - 01/10/2005
			- Modification for PXA270 MAINSTONE.
			- Modified dmfe_tx_done().
			- Add dmfe_timeout().
V2.01	10/07/2005	Modified dmfe_timer()
			Dected network speed 10/100M
V2.02	10/12/2005	Use link change to chage db->Speed
			dmfe_open() wait for Link OK  
V2.03	11/22/2005	Power-off and Power-on PHY in dmfe_init()
			support IOL
*/

#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif

#include <linux/config.h>
#include <linux/init.h>				
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/dma.h>
#include <linux/spinlock.h>
//#include <linux/crc32.h>  //tj1205

#include <asm/io.h>
#include <asm/irq.h>


/* Board/System/Debug information/definition ---------------- */

#define DM9KS_ID		0x90000A46
#define DM9010_ID		0x90100A46
/*-------register name-----------------------*/
#define DM9KS_NCR		0x00	/* Network control Reg.*/
#define DM9KS_NSR		0x01	/* Network Status Reg.*/
#define DM9KS_TCR		0x02	/* TX control Reg.*/
#define DM9KS_RXCR		0x05	/* RX control Reg.*/
#define DM9KS_BPTR		0x08
#define DM9KS_EPCR		0x0b
#define DM9KS_EPAR		0x0c
#define DM9KS_EPDRL		0x0d
#define DM9KS_EPDRH		0x0e
#define DM9KS_GPR		0x1f	/* General purpose register */
#define DM9KS_TCR2		0x2d
#define DM9KS_SMCR		0x2f 	/* Special Mode Control Reg.*/
#define DM9KS_ETXCSR		0x30	/* Early Transmit control/status Reg.*/
#define	DM9KS_TCCR		0x31	/* Checksum cntrol Reg. */
#define DM9KS_RCSR		0x32	/* Receive Checksum status Reg.*/
#define DM9KS_MRCMDX		0xf0
#define DM9KS_MRCMD		0xf2
#define DM9KS_MDRAL		0xf4
#define DM9KS_MDRAH		0xf5
#define DM9KS_MWCMD		0xf8
#define DM9KS_TXPLL		0xfc
#define DM9KS_TXPLH		0xfd
#define DM9KS_ISR		0xfe
#define DM9KS_IMR		0xff
/*---------------------------------------------*/
#define DM9KS_REG05		0x30	/* SKIP_CRC/SKIP_LONG */ 
#define DM9KS_REGFF		0xA3	/* IMR */
#define DM9KS_DISINTR		0x80

#define DM9KS_PHY		0x40	/* PHY address 0x01 */
#define DM9KS_PKT_RDY		0x01	/* Packet ready to receive */

#define DM9KS_MIN_IO		0xd0000000	//tj1204 0xd0000000
#define DM9KS_MAX_IO		0xd0000370
#define DM9K_IRQ		IRQ_CS8900 

#define DM9KS_VID_L		0x28
#define DM9KS_VID_H		0x29
#define DM9KS_PID_L		0x2A
#define DM9KS_PID_H		0x2B

#define DM9KS_RX_INTR		0x01
#define DM9KS_TX_INTR		0x02
#define DM9KS_LINK_INTR		0x20

#define DM9KS_DWORD_MODE	1
#define DM9KS_BYTE_MODE		2
#define DM9KS_WORD_MODE		0

#define TRUE			1
#define FALSE			0
/* Number of continuous Rx packets */
#define CONT_RX_PKT_CNT	32 

#define DMFE_TIMER_WUT  jiffies+(HZ*5)	/* timer wakeup time : 5 second */

#if defined(DM9KS_DEBUG)
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dmfe_debug||dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#else
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#endif

#undef inb
#undef outb
#undef inw
#undef outw
#undef inl
#undef outl


typedef struct _RX_DESC
{
	u8 rxbyte;
	u8 status;
	u16 length;
}RX_DESC;

typedef union{
	u8 buf[4];
	RX_DESC desc;
} rx_t;

enum DM9KS_PHY_mode {
	DM9KS_10MHD   = 0, 
	DM9KS_100MHD  = 1, 
	DM9KS_10MFD   = 4,
	DM9KS_100MFD  = 5, 
	DM9KS_AUTO    = 8, 
};

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
 
	u32 reset_counter;		/* counter: RESET */ 
	u32 reset_tx_timeout;		/* RESET caused by TX Timeout */ 

	u32 io_addr;			/* Register I/O base address */
	u32 io_data;			/* Data I/O address */
	int tx_pkt_cnt;

	u8 op_mode;			/* PHY operation mode */
	u8 io_mode;			/* 0:word, 2:byte */
	u8 device_wait_reset;		/* device state */
	u8 Speed;			/* current speed */

	int cont_rx_pkt_cnt;/* current number of continuos rx packets  */
	struct timer_list timer;
	struct net_device_stats stats;
	unsigned char srom[128];
	spinlock_t lock;

} board_info_t;
/* Global variable declaration ----------------------------- */
/*static int dmfe_debug = 0;*/
static struct net_device * dmfe_dev = NULL;

/* For module input parameter */
static int mode       = DM9KS_AUTO;
static int media_mode = DM9KS_AUTO;
static u8  irq        = DM9K_IRQ;
static u32 iobase     = DM9KS_MIN_IO;
static u32 lanBase	  = DM9KS_MIN_IO;

/* function declaration ------------------------------------- */
int dmfe_probe(struct net_device *);
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static void dmfe_tx_done(unsigned long);
static void dmfe_packet_receive(struct net_device *);
static int dmfe_stop(struct net_device *);
static struct net_device_stats * dmfe_get_stats(struct net_device *); 
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
static void dmfe_interrupt(int , void *, struct pt_regs *);
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u8 ior(board_info_t *, int);
static void iow(board_info_t *, int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);
static u16 read_srom_word(board_info_t *, int);
static void dm9000_hash_table(struct net_device *);
static void dmfe_timeout(struct net_device *);
static void dmfe_reset(struct net_device *);

#if defined(CHECKSUM)
static u8 check_rx_ready(u8);
#endif


/* DM9000 network baord routine ---------------------------- */

static u8 inb(u16 addr);
static void outb(u8 value, u16 addr);
static u16 inw(u16 addr);
static void outw(u16 value, u16 addr);
static u32 inl(u16 addr);
static void outl(u32 value, u16 addr);

static u8 inb(volatile u16 addr)
{   
	return(*(volatile u8 *)(lanBase+addr));
}

static void outb(volatile u8 value, volatile u16 addr)
{   
	*(volatile u8 *)(lanBase+addr) = value;
}

static u16 inw(volatile u16 addr)
{   
	return(*(volatile u16 *)(lanBase+addr));
}

static void outw(volatile u16 value, volatile u16 addr)
{   
	*(volatile u16 *)(lanBase+addr) = value;
}

static u32 inl(volatile u16 addr)
{   
	return(*(volatile u32 *)(lanBase+addr));
}

static void outl(volatile u32 value, volatile u16 addr)
{   
	*(volatile u32 *)(lanBase+addr) = value;
}                                                                                                


/*
  Search DM9000 board, allocate space and register it
*/

struct net_device * __init dmfe_probe1(void)
{
	struct net_device *dev;
	int err;

	dev = init_etherdev(NULL, sizeof(struct board_info));
	ether_setup(dev);		


	if(!dev)
		return ERR_PTR(-ENOMEM);

     	SET_MODULE_OWNER(dev);
	err = dmfe_probe(dev);
	if (err)
		goto out;

	return dev;
out1:
	release_region(dev->base_addr,2);
out:

	return ERR_PTR(err);
}

int __init dmfe_probe(struct net_device *dev)
{
	struct board_info *db;    /* Point a board information structure */
	u32 id_val;
	u16 i, cmd_select,dm9000_found = FALSE;

			
    BWSCON = (BWSCON & ~(BWSCON_ST3 | BWSCON_WS3 | BWSCON_DW3)) |
    //(BWSCON_ST3 | BWSCON_WS3 | BWSCON_DW(3, BWSCON_DW_16));
    (BWSCON_DW(3, BWSCON_DW_16));  //job20070201
   /* BANKCON3= BANKCON_Tacs0 | BANKCON_Tcos4 | BANKCON_Tacc14 |
    BANKCON_Toch1 | BANKCON_Tcah4 | BANKCON_Tacp6 | BANKCON_PMC16; //031201 1data --> 16data/page*/
    BANKCON3=0x2410;  //lgl20070131
    
	printk("\n BWSCON 0x%08x\n",BWSCON);  //lgl20070131
	printk("\n BANKCON3 0x%08x\n",BANKCON3);  //lgl20070131

    set_external_irq(IRQ_CS8900, EXT_RISING_EDGE, GPIO_PULLUP_DIS);	/*tj1204*/

	DMFE_DBUG(0, "dmfe_probe()",0);

	/* Search All DM9000 serial NIC */
	do {
		
		outb(DM9KS_VID_L, iobase);
		for(cmd_select = 1; cmd_select < 0x4000; )
		{
			id_val = inb(iobase + cmd_select);
			printk("<DM9KS> cmd_select : %02x, VID: %02x \n",cmd_select, id_val);
			if(id_val == 0x46) break;
			cmd_select = cmd_select << 1;
		}
		
		outb(DM9KS_VID_L, iobase);
		id_val = inb(iobase + cmd_select);
		outb(DM9KS_VID_H, iobase);
		id_val |= inb(iobase + cmd_select) << 8;
		outb(DM9KS_PID_L, iobase);
		id_val |= inb(iobase + cmd_select) << 16;
		outb(DM9KS_PID_H, iobase);
		id_val |= inb(iobase + cmd_select) << 24;

		if (id_val == DM9KS_ID || id_val == DM9010_ID) {
			

			dev = init_etherdev(dev, 0);
			ether_setup(dev);
			
			SET_MODULE_OWNER(dev);

			/* Request IO from system */
			if(!request_region(iobase, 2, dev->name))
				return -ENODEV;

			printk("<DM9KS> I/O: %x, VID: %x \n",iobase, id_val);
			dm9000_found = TRUE;

			/* Allocated board information structure */
			
			db = (struct board_info *) kmalloc(sizeof(*db), GFP_KERNEL);
			memset(db, 0, sizeof(*db));
			dev->priv   = db;   /* link device and board info */

			dmfe_dev    = dev;
			db->io_addr  = iobase;
			db->io_data = iobase + cmd_select;
			/* driver system function */
				
			dev->base_addr 		= iobase;
			dev->irq 		= irq;
			dev->open 		= &dmfe_open;
			dev->hard_start_xmit 	= &dmfe_start_xmit;
			dev->watchdog_timeo	= HZ;	
			dev->tx_timeout		= dmfe_timeout;
			dev->stop 		= &dmfe_stop;
			dev->get_stats 		= &dmfe_get_stats;
			dev->set_multicast_list = &dm9000_hash_table;
			dev->do_ioctl 		= &dmfe_do_ioctl;

			printk("IRQ %d", dev->irq);	//tj1204
			
#if defined(CHECKSUM)
			dev->features = dev->features | NETIF_F_NO_CSUM;
#endif
			/* Read SROM content */
			for (i=0; i<64; i++)
				((u16 *)db->srom)[i] = read_srom_word(db, i);

			/* Set Node Address 
			for (i=0; i<6; i++)
				dev->dev_addr[i] = db->srom[i];*/
		}//end of if()

/*************tj set mac***************/		
    dev->dev_addr[0] = 0x00;
    dev->dev_addr[1] = 0x00;
    dev->dev_addr[2] = 0xc0;
    dev->dev_addr[3] = 0xff;
    dev->dev_addr[4] = 0xee;
    dev->dev_addr[5] = 0x08;
    
/****************************************/    
		iobase += 0x10;
	}while(!dm9000_found && iobase <= DM9KS_MAX_IO);

	return dm9000_found ? 0:-ENODEV;
}


/*
  Open the interface.
  The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	u8 reg_nsr;
	int i;
	DMFE_DBUG(0, "dmfe_open", 0);
	
	if (request_irq(dev->irq,&dmfe_interrupt,SA_SHIRQ,dev->name,dev)) 
		return -EAGAIN;

	/* Initilize DM910X board */
	dmfe_init_dm9000(dev);
 
	/* Init driver variable */
	db->reset_counter 	= 0;
	db->reset_tx_timeout 	= 0;
	db->cont_rx_pkt_cnt	= 0;
	
	/* check link state and media speed */
	db->Speed =10;
	i=0;
	do {
		reg_nsr = ior(db,0x1);
		if(reg_nsr & 0x40) /* link OK!! */
		{
			/* wait for detected Speed */
			mdelay(200);
			reg_nsr = ior(db,0x1);
			if(reg_nsr & 0x80)
				db->Speed =10;
			else
				db->Speed =100;
			break;
		}
		i++;
		mdelay(1);
	}while(i<3000);	/* wait 3 second  */
	//printk("i=%d  Speed=%d\n",i,db->Speed);	
	/* set and active a timer process */
	init_timer(&db->timer);
	db->timer.expires 	= DMFE_TIMER_WUT * 2;
	db->timer.data 		= (unsigned long)dev;
	db->timer.function 	= &dmfe_timer;
	add_timer(&db->timer);	//Move to DM9000 initiallization was finished.
 	
	netif_start_queue(dev);

	return 0;
}

/* Set PHY operationg mode
*/
static void set_PHY_mode(board_info_t *db)
{
	u16 phy_reg0 = 0x1200;		/* Auto-negotiation & Restart Auto-negotiation */
	u16 phy_reg4 = 0x01e1;		/* Default flow control disable*/

	if ( !(db->op_mode & DM9KS_AUTO) ) // op_mode didn't auto sense */
	{ 
		switch(db->op_mode) {
			case DM9KS_10MHD:  phy_reg4 = 0x21; 
                        	           phy_reg0 = 0x1000;
					   break;
			case DM9KS_10MFD:  phy_reg4 = 0x41; 
					   phy_reg0 = 0x1100;
                                	   break;
			case DM9KS_100MHD: phy_reg4 = 0x81; 
					   phy_reg0 = 0x3000;
				    	   break;
			case DM9KS_100MFD: phy_reg4 = 0x101; 
					   phy_reg0 = 0x3100;
				   	   break;
			default: 
					   break;
		} // end of switch
	} // end of if
	phy_write(db, 0, phy_reg0);
	phy_write(db, 4, phy_reg4);
}

/* 
	Initilize dm9000 board
*/
static void dmfe_init_dm9000(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_init_dm9000()", 0);

	/* set the internal PHY power-on, GPIOs normal, and wait 2ms */
	iow(db, DM9KS_GPR, 1); 	/* Power-Down PHY */
	udelay(500);
	iow(db, DM9KS_GPR, 0);	/* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
	udelay(20);		/* wait 2ms for PHY power-on ready */

	/* do a software reset and wait 20us */
	iow(db, DM9KS_NCR, 3);
	udelay(20);		/* wait 20us at least for software reset ok */
	iow(db, DM9KS_NCR, 3);	/* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on */
	udelay(20);		/* wait 20us at least for software reset ok */

	/* I/O mode */
	db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */

	/* Set PHY */
	db->op_mode = media_mode;
	set_PHY_mode(db);

	/* Program operating register */
	iow(db, DM9KS_NCR, 0);
	iow(db, DM9KS_TCR, 0);		/* TX Polling clear */
	iow(db, DM9KS_BPTR, 0x3f);	/* Less 3kb, 600us */
	iow(db, DM9KS_SMCR, 0);		/* Special Mode */
	iow(db, DM9KS_NSR, 0x2c);	/* clear TX status */
	iow(db, DM9KS_ISR, 0x0f); 	/* Clear interrupt status */
	iow(db, 0x2d, 0x80);        /* set led mode */
	
	printk("[dmfe_init_dm9000] reg 0x39 = %02x \n", ior(db, 0x39));
	iow(db, 0x39, 0x00);
	printk("[dmfe_init_dm9000] set reg 0x39 = %02x \n", ior(db, 0x39));
	

	/* Added by jackal at 03/29/2004 */
#if defined(CHECKSUM)
	iow(db, DM9KS_TCCR, 0x07);	/* TX UDP/TCP/IP checksum enable */
	iow(db, DM9KS_RCSR, 0x02);	/*Receive checksum enable */
#endif

#if defined(ETRANS)
	iow(db, DM9KS_ETXCSR, 0x83);
#endif
 
	/* Set address filter table */
	dm9000_hash_table(dev);

	/* Activate DM9000A/DM9010 */
	iow(db, DM9KS_RXCR, DM9KS_REG05 | 1);	/* RX enable */
	iow(db, DM9KS_IMR, DM9KS_REGFF); 	// Enable TX/RX interrupt mask
 
	/* Init Driver variable */
	db->tx_pkt_cnt 		= 0;
		
	netif_carrier_on(dev);
	spin_lock_init(&db->lock);

}

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	char * data_ptr;
	int i, tmplen;
	
#if 0
	if (db->tx_pkt_cnt >= 1) return 1;
#else
	if(db->Speed == 10)
		{if (db->tx_pkt_cnt >= 1) return 1;}
	else
		{if (db->tx_pkt_cnt >= 2) return 1;}
#endif
	
	/* packet counting */
	db->tx_pkt_cnt++;

	db->stats.tx_packets++;
	db->stats.tx_bytes+=skb->len;
#if 0
	netif_stop_queue(dev);
#else	
	if (db->Speed == 10)
		{if (db->tx_pkt_cnt >= 1) netif_stop_queue(dev);}
	else
		{if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev);}
#endif

	/* Disable all interrupt */
	iow(db, DM9KS_IMR, DM9KS_DISINTR);

	/* Set TX length to reg. 0xfc & 0xfd */
	iow(db, DM9KS_TXPLL, (skb->len & 0xff));
	iow(db, DM9KS_TXPLH, (skb->len >> 8) & 0xff);

	/* Move data to TX SRAM */
	data_ptr = (char *)skb->data;
	
	outb(DM9KS_MWCMD, db->io_addr); // Write data into SRAM trigger
	switch(db->io_mode)
	{
		case DM9KS_BYTE_MODE:
			for (i = 0; i < skb->len; i++)
				outb((data_ptr[i] & 0xff), db->io_data);
			break;
		case DM9KS_WORD_MODE:
			tmplen = (skb->len + 1) / 2;
			for (i = 0; i < tmplen; i++)
         			outw(((u16 *)data_ptr)[i], db->io_data);
         		break;
         	case DM9KS_DWORD_MODE:
         		tmplen = (skb->len + 3) / 4;			
			for (i = 0; i< tmplen; i++)
				outl(((u32 *)data_ptr)[i], db->io_data);
			break;
	}
	
#if !defined(ETRANS)
	/* Issue TX polling command */
	iow(db, DM9KS_TCR, 0x1); /* Cleared after TX complete*/
#endif

	/* Saved the time stamp */
	dev->trans_start = jiffies;
	db->cont_rx_pkt_cnt =0;

	/* Free this SKB */