并行匹配滤波器程序.txt

并行匹配滤波器

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mf_parallel_tap is 
  generic( iINDatawidth:integer:=8;
           iOUTDatawidth:integer:=16;
           iOVERsamplerate:integer:=16);
      port( INcode:in std_logic;
            INdata:in std_logic_vector(iINDatawidth-1 downto 0 );
            Prevtap:in std_logic_vector(iOUTDatawidth-1 downto 0 );
            sysclk: in std_logic;
            sysrst: in std_logic;
            OUTcode:out std_logic;
            result: out std_logic_vector(iOUTDatawidth-1 downto 0));
    
   end mf_parallel_tap;
 architecture virtex of mf_parallel_tap is
    type PipelineArray is array (iOverSamplerate-2 downto 0) of signed(iOUTDatawidth-1 downto 0);
    signal sINData:signed(iINDatawidth-1 downto 0);
    signal sPrevtap:signed(iOUTDatawidth-1 downto 0);
    signal sADDsubout:signed(iOUTDatawidth-1 downto 0);
    signal spipe :pipelineArray;
    signal iCodedata:std_logic;
    begin 
    ----------------------------------------------
    -- setup input data types
    ----------------------------------------------
    sINData<=signed(INdata);
    sPrevtap<=signed(Prevtap);
    ----------------------------------------------
    Singletap:process(sysclk,sysRst)
    -----------------------------------------------
    begin 
      if (sysrst='1') then
        sAddSubout<=(others=>'0');
        icodedata<='0';
      elsif (sysclk'event and sysclk='1') then
        iCodedata<=incode;
        if (icodedata='0') then 
           sAddsubout<=sPrevtap+sindata;
        else
        saddsubout<=sPrevtap-sindata;
        end if;
      end if;
   end process singletap;
   ----------------------------------------------
   generatepipeline:process(sysclk)
   ----------------------------------------------
   begin 
    if (sysclk'event and sysclk='1') then
      spipe<=spipe(ioversamplerate-3 downto spipe'low)&saddsubout;
    end if;
   end process generatepipeline;
  ------------------------------------------------
 --sourse output data
 -------------------------------------------------
  feedthrucode:outcode<=icodedata;
  generateresult:result<=std_logic_vector(spipe(ioversamplerate-2));
  end virtex;
library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
  entity mf is 
  generic( iINDatawidth:integer:=8;
           iOUTDatawidth:integer:=16;
           iOVERsamplerate:integer:=16;
           iNumofchips:integer:=128);
    port( incode:in std_logic;
          INdata:in std_logic_vector(iINDatawidth-1 downto 0 );
            sysclk: in std_logic;
            sysrst: in std_logic;
            result: out std_logic_vector(iOUTDatawidth-1 downto 0));
  end mf;
  architecture virtex of mf is
     type resultarray is array (inumofchips-1 downto 0) of std_logic_vector(ioutdatawidth-1 downto 0);
  signal zero :std_logic_vector(ioutdatawidth-1 downto 0);
  signal ioutcode:std_logic_vector(inumofchips-1 downto 0);
  signal iresult:resultarray;
  component mf_parallel_tap
    generic(iINDatawidth:integer:=8;
           iOUTDatawidth:integer:=16;
           iOVERsamplerate:integer:=16);

    port(   INcode:in std_logic;
            INdata:in std_logic_vector(iINDatawidth-1 downto 0 );
            Prevtap:in std_logic_vector(iOUTDatawidth-1 downto 0 );
            sysclk: in std_logic;
            sysrst: in std_logic;
            OUTcode:out std_logic;
            result: out std_logic_vector(iOUTDatawidth-1 downto 0));
  end component;
  begin
   zero<=(others=>'0');
   firsttap:mf_parallel_tap
   generic map(
    iindatawidth=>iindatawidth,
    ioutdatawidth=>ioutdatawidth,
    iOVERsamplerate=>iOVERsamplerate
    )
   port map(
     incode=>incode,
     indata=>indata,
     prevtap=>zero,
     sysclk=>sysclk,
     sysrst=>sysrst,
     outcode=>ioutcode(0),
     result=>iresult(0)
     );
   insttaps: for I in 1 to inumofchips-1 generate
   taps:mf_parallel_tap
   generic map(
    iindatawidth=>iindatawidth,
    ioutdatawidth=>ioutdatawidth,
    ioversamplerate=>ioversamplerate
    )
   port map(
     incode=>ioutcode(I-1),
     indata=>indata,
     prevtap=>iresult(I-1),
     sysclk=>sysclk,
     sysrst=>sysrst,
     outcode=>ioutcode(I),
     result=>iresult(I)
      );
    end generate insttaps;
  generateresult:result<=iresult(inumofchips-1);
  end virtex;