📄 mokuai.mdl
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Model {
Name "mokuai"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Fri Apr 13 10:38:40 2007"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "Xiao hei"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sat Apr 21 11:01:06 2007"
ModelVersionFormat "1.%<AutoIncrement:3>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
ShowAdditionalParam off
AllPortsSameDT on
OutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
}
Block {
BlockType Memory
X0 "0"
InheritSampleTime off
LinearizeMemory off
RTWStateStorageClass "Auto"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "mokuai"
Location [165, 275, 701, 917]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Inport
Name "in_1"
Position [100, 135, 120, 155]
ShowName off
}
Block {
BlockType Inport
Name "in_2"
Position [100, 85, 120, 105]
ShowName off
Port "2"
}
Block {
BlockType Memory
Name "Memory"
Position [110, 200, 140, 230]
}
Block {
BlockType Memory
Name "Memory1"
Position [265, 205, 295, 235]
}
Block {
BlockType Memory
Name "Memory2"
Position [410, 205, 440, 235]
}
Block {
BlockType Logic
Name "XOR\nExclusive OR"
Ports [2, 1]
Position [180, 185, 220, 225]
Operator "XOR"
ShowAdditionalParam on
AllPortsSameDT off
OutDataTypeMode "Specify via dialog"
}
Block {
BlockType Logic
Name "XOR\nExclusive OR1"
Ports [2, 1]
Position [335, 190, 375, 230]
Operator "XOR"
ShowAdditionalParam on
AllPortsSameDT off
OutDataTypeMode "Specify via dialog"
}
Block {
BlockType Outport
Name "out_1"
Position [485, 210, 505, 230]
ShowName off
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_2"
Position [485, 135, 505, 155]
ShowName off
Port "2"
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_3"
Position [485, 85, 505, 105]
ShowName off
Port "3"
InitialOutput "0"
}
Line {
SrcBlock "in_2"
SrcPort 1
Points [165, 0]
Branch {
Points [0, 105]
DstBlock "XOR\nExclusive OR1"
DstPort 1
}
Branch {
DstBlock "out_3"
DstPort 1
}
}
Line {
SrcBlock "in_1"
SrcPort 1
Points [35, 0]
Branch {
Points [0, 50]
DstBlock "XOR\nExclusive OR"
DstPort 1
}
Branch {
DstBlock "out_2"
DstPort 1
}
}
Line {
SrcBlock "Memory"
SrcPort 1
DstBlock "XOR\nExclusive OR"
DstPort 2
}
Line {
SrcBlock "XOR\nExclusive OR"
SrcPort 1
Points [10, 0; 0, 15]
DstBlock "Memory1"
DstPort 1
}
Line {
SrcBlock "Memory1"
SrcPort 1
DstBlock "XOR\nExclusive OR1"
DstPort 2
}
Line {
SrcBlock "XOR\nExclusive OR1"
SrcPort 1
Points [5, 0; 0, 10]
DstBlock "Memory2"
DstPort 1
}
Line {
SrcBlock "Memory2"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 75; -385, 0; 0, -80]
DstBlock "Memory"
DstPort 1
}
Branch {
DstBlock "out_1"
DstPort 1
}
}
}
}
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