led_water.syr

简易流水灯实验

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: LED_WATER.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "LED_WATER.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "LED_WATER"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : LED_WATER
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : LED_WATER.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "led_water.v" in library work
Module <LED_WATER> compiled
WARNING:HDLCompilers:258 - "led_water.v" line 4 Range on redeclaration of 'LED' overrides range on output declaration at "led_water.v" line 3 
No errors in compilation
Analysis of file <"LED_WATER.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:258 - "led_water.v" line 4 Range on redeclaration of 'LED' overrides range on output declaration at "led_water.v" line 3 
Analyzing top module <LED_WATER>.
Module <LED_WATER> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <LED_WATER>.
    Related source file is "led_water.v".
    Found 5-bit register for signal <LED>.
    Found 24-bit adder for signal <$old_buffer_1>.
    Found 24-bit up counter for signal <buffer>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <LED_WATER> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 24-bit adder                                          : 1
# Counters                                             : 1
 24-bit up counter                                     : 1
# Registers                                            : 1
 5-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 24-bit adder                                          : 1
# Counters                                             : 1
 24-bit up counter                                     : 1
# Registers                                            : 5
 Flip-Flops                                            : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx.

Optimizing unit <LED_WATER> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block LED_WATER, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : LED_WATER.ngr
Top Level Output File Name         : LED_WATER
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 6

Cell Usage :
# BELS                             : 156
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 23
#      LUT1_L                      : 23
#      LUT2_L                      : 2
#      LUT4                        : 10
#      LUT4_L                      : 2
#      MUXCY                       : 46
#      VCC                         : 1
#      XORCY                       : 46
# FlipFlops/Latches                : 29
#      FD                          : 24
#      FDE                         : 5
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      44  out of   3584     1%  
 Number of Slice Flip Flops:            29  out of   7168     0%  
 Number of 4 input LUTs:                60  out of   7168     0%  
 Number of bonded IOBs:                  6  out of    141     4%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 29    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 8.510ns (Maximum Frequency: 117.516MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.388ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 8.510ns (frequency: 117.516MHz)
  Total number of paths / destination ports: 1820 / 34
-------------------------------------------------------------------------
Delay:               8.510ns (Levels of Logic = 19)
  Source:            buffer_1 (FF)
  Destination:       LED_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: buffer_1 to LED_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   1.040  buffer_1 (buffer_1)
     LUT1_L:I0->LO         1   0.479   0.000  buffer_1_rt (buffer_1_rt)
     MUXCY:S->O            1   0.435   0.000  LED_WATER__old_buffer_1<1>cy (LED_WATER__old_buffer_1<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<2>cy (LED_WATER__old_buffer_1<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<3>cy (LED_WATER__old_buffer_1<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<4>cy (LED_WATER__old_buffer_1<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<5>cy (LED_WATER__old_buffer_1<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<6>cy (LED_WATER__old_buffer_1<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<7>cy (LED_WATER__old_buffer_1<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<8>cy (LED_WATER__old_buffer_1<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<9>cy (LED_WATER__old_buffer_1<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<10>cy (LED_WATER__old_buffer_1<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<11>cy (LED_WATER__old_buffer_1<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<12>cy (LED_WATER__old_buffer_1<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<13>cy (LED_WATER__old_buffer_1<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  LED_WATER__old_buffer_1<14>cy (LED_WATER__old_buffer_1<14>_cyo)
     XORCY:CI->O           1   0.786   0.704  LED_WATER__old_buffer_1<15>_xor (_old_buffer_1<15>)
     LUT4:I3->O            1   0.479   0.704  _n0000541_SW0_SW0 (N83)
     LUT4_L:I3->LO         1   0.479   0.270  _n0000541_SW0 (N81)
     LUT4:I1->O            5   0.479   0.783  _n0000157 (_n0000)
     FDE:CE                    0.524          LED_0
    ----------------------------------------
    Total                      8.510ns (5.009ns logic, 3.501ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              6.388ns (Levels of Logic = 1)
  Source:            LED_3 (FF)
  Destination:       LED<3> (PAD)
  Source Clock:      CLK rising

  Data Path: LED_3 to LED<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.626   0.853  LED_3 (LED_3)
     OBUF:I->O                 4.909          LED_3_OBUF (LED<3>)
    ----------------------------------------
    Total                      6.388ns (5.535ns logic, 0.853ns route)
                                       (86.7% logic, 13.3% route)

=========================================================================
CPU : 11.27 / 12.47 s | Elapsed : 11.00 / 12.00 s
 
--> 

Total memory usage is 112276 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)