led_water.v

来自「简易流水灯实验」· Verilog 代码 · 共 20 行

module LED_WATER ( CLK, LED );
input CLK;
output [3:0] LED; 
reg [4:0] LED;
reg [23:0] buffer;
initial
LED=5'b11111;
always @ ( posedge CLK ) 
begin
buffer = buffer +1;
if ( buffer == 24'd12500000)
  begin
LED=LED<<1;
if ( LED==5'b00000 )
LED=5'b11111; 
end 
end
endmodule