led_water.twr

简易流水灯实验

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise waterlight.ise -intstyle ise -e 3 -l 3 -s 5 -xml
LED_WATER LED_WATER.ncd -o LED_WATER.twr LED_WATER.pcf


Design file:              led_water.ncd
Physical constraint file: led_water.pcf
Device,speed:             xc3s400,-5 (PRODUCTION 1.37 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
LED<0>      |    7.968(R)|CLK_BUFGP         |   0.000|
LED<1>      |    7.317(R)|CLK_BUFGP         |   0.000|
LED<2>      |    7.996(R)|CLK_BUFGP         |   0.000|
LED<3>      |    7.342(R)|CLK_BUFGP         |   0.000|
LED<4>      |    6.407(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    7.777|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sun May 13 12:24:42 2007
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Peak Memory Usage: 105 MB