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📄 counvolu.mdl

📁 卷积码在AWGN信道下的实现 包括simulink文件与.m文件
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    Block {
      BlockType		      FrameConversion
      OutFrame		      "Frame based"
    }
    Block {
      BlockType		      Ground
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Mux
      Inputs		      "4"
      DisplayOption	      "none"
      BusObject		      "BusObject"
      NonVirtualBus	      off
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Advanced Sim. Parameters)"
      LogicDataType	      "uint(8)"
      ZeroCross		      on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      ToWorkspace
      VariableName	      "simulink_output"
      MaxDataPoints	      "1000"
      Decimation	      "1"
      SampleTime	      "0"
      FixptAsFi		      off
    }
    Block {
      BlockType		      ZeroOrderHold
      SampleTime	      "1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "counvolu"
    Location		    [166, 94, 937, 723]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "AWGN\nChannel"
      Ports		      [1, 1]
      Position		      [550, 74, 630, 116]
      SourceBlock	      "commchan2/AWGN\nChannel"
      SourceType	      "AWGN Channel"
      ShowPortLabels	      on
      seed		      "18233"
      noiseMode		      "Signal to noise ratio  (SNR)"
      EbNodB		      "10"
      EsNodB		      "10"
      SNRdB		      "0"
      bitsPerSym	      "1"
      Ps		      "1"
      Tsym		      "12345"
      variance		      "errB"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Reference
      Name		      "BPSK\nModulator\nBaseband"
      Ports		      [1, 1]
      Position		      [330, 66, 405, 114]
      SourceBlock	      "commdigbbndpm2/BPSK\nModulator\nBaseband"
      SourceType	      "BPSK Modulator Baseband"
      ShowPortLabels	      on
      Ph		      "0"
      numSamp		      "1"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Bernoulli Binary\nGenerator"
      Ports		      [0, 1]
      Position		      [15, 53, 95, 97]
      FontName		      "Arial"
      SourceBlock	      "commrandsrc2/Bernoulli Binary\nGenerator"
      SourceType	      "Bernoulli Binary Generator"
      ShowPortLabels	      on
      P			      "0.5"
      seed		      "435345"
      Ts		      "1"
      frameBased	      on
      sampPerFrame	      "10"
      orient		      off
    }
    Block {
      BlockType		      ComplexToRealImag
      Name		      "Complex to\nReal-Imag"
      Ports		      [1, 1]
      Position		      [665, 355, 695, 385]
      Orientation	      "left"
      Output		      "Real"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Convolutional\nEncoder"
      Ports		      [1, 1]
      Position		      [160, 50, 280, 110]
      FontSize		      10
      SourceBlock	      "commcnvcod2/Convolutional\nEncoder"
      SourceType	      "Convolutional Encoder"
      trellis		      "poly2trellis(9, [753 561])"
      reset		      "None"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Demux
      Name		      "Demux"
      Ports		      [1, 3]
      Position		      [310, 291, 315, 329]
      BackgroundColor	      "black"
      ShowName		      off
      Outputs		      "3"
      DisplayOption	      "bar"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Display
      Name		      "Display"
      Ports		      [1]
      Position		      [445, 305, 535, 335]
      Decimation	      "1"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Error Rate\nCalculation"
      Ports		      [2, 1]
      Position		      [140, 242, 215, 293]
      SourceBlock	      "commsink2/Error Rate\nCalculation"
      SourceType	      "Error Rate Calculation"
      N			      "96"
      st_delay		      "0"
      cp_mode		      "Entire frame"
      subframe		      "[]"
      PMode		      "Port"
      WsName		      "ErrorVec"
      RsMode2		      off
      stop		      on
      numErr		      "100"
      maxBits		      "1e6"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
      Port {
	PortType		0
	PortNumber		2
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Mux
      Name		      "Mux"
      Ports		      [3, 1]
      Position		      [345, 291, 350, 329]
      ShowName		      off
      Inputs		      "3"
      DisplayOption	      "bar"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
      Port {
	PortType		0
	PortNumber		2
	ShowSigGenPortName	on
      }
      Port {
	PortType		0
	PortNumber		3
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      ToWorkspace
      Name		      "To Workspace1"
      Position		      [475, 15, 535, 45]
      VariableName	      "simout"
      MaxDataPoints	      "inf"
      SampleTime	      "-1"
      SaveFormat	      "Array"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      ToWorkspace
      Name		      "To Workspace2"
      Position		      [360, 235, 420, 265]
      VariableName	      "s"
      MaxDataPoints	      "inf"
      SampleTime	      "-1"
      SaveFormat	      "Array"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      ToWorkspace
      Name		      "To Workspace4"
      Position		      [640, 175, 700, 205]
      VariableName	      "simout3"
      MaxDataPoints	      "inf"
      SampleTime	      "-1"
      SaveFormat	      "Array"
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Viterbi Decoder"
      Ports		      [1, 1]
      Position		      [495, 355, 615, 415]
      Orientation	      "left"
      FontSize		      10
      SourceBlock	      "commcnvcod2/Viterbi Decoder"
      SourceType	      "Viterbi Decoder"
      trellis		      "poly2trellis(9, [753 561])"
      dectype		      "Unquantized"
      nsdecb		      "4"
      tbdepth		      "96"
      opmode		      "Continuous"
      reset		      off
      Port {
	PortType		0
	PortNumber		1
	ShowSigGenPortName	on
      }
    }
    Line {
      SrcBlock		      "Demux"
      SrcPort		      2
      DstBlock		      "Mux"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Demux"
      SrcPort		      3
      DstBlock		      "Mux"
      DstPort		      3
    }
    Line {
      Labels		      [3, 0]
      SrcBlock		      "Viterbi Decoder"
      SrcPort		      1
      Points		      [-30, 0; 0, -25; -350, 0; 0, -80]
      DstBlock		      "Error Rate\nCalculation"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Mux"
      SrcPort		      1
      Points		      [75, 0]
      DstBlock		      "Display"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Error Rate\nCalculation"
      SrcPort		      1
      Points		      [45, 0; 0, 40]
      DstBlock		      "Demux"
      DstPort		      1
    }
    Line {
      SrcBlock		      "AWGN\nChannel"
      SrcPort		      1
      Points		      [0, -15; -20, 0]
      Branch {
	Points			[0, 110]
	DstBlock		"To Workspace4"
	DstPort			1
      }
      Branch {
	Points			[25, 0; 0, -5; 70, 0]
	DstBlock		"Complex to\nReal-Imag"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "BPSK\nModulator\nBaseband"
      SrcPort		      1
      Points		      [30, 0]
      Branch {
	Labels			[1, 0]
	Points			[95, 0]
	DstBlock		"AWGN\nChannel"
	DstPort			1
      }
      Branch {
	Points			[0, -60]
	DstBlock		"To Workspace1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Demux"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	DstBlock		"Mux"
	DstPort			1
      }
      Branch {
	Points			[0, -50]
	DstBlock		"To Workspace2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Convolutional\nEncoder"
      SrcPort		      1
      Points		      [10, 0; 0, 10]
      DstBlock		      "BPSK\nModulator\nBaseband"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Bernoulli Binary\nGenerator"
      SrcPort		      1
      Points		      [25, 0]
      Branch {
	DstBlock		"Error Rate\nCalculation"
	DstPort			1
      }
      Branch {
	Points			[20, 0]
	DstBlock		"Convolutional\nEncoder"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Complex to\nReal-Imag"
      SrcPort		      1
      Points		      [-15, 0; 0, 15]
      DstBlock		      "Viterbi Decoder"
      DstPort		      1
    }
  }
}

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