📄 eeprom.lst
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C51 COMPILER V7.06 EEPROM 12/15/2005 23:22:10 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE EEPROM
OBJECT MODULE PLACED IN EEPROM.OBJ
COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE EEPROM.c LARGE BROWSE DEBUG OBJECTEXTEND
stmt level source
1 #include <C8051F020.h>
2 #include "EEPROM.h"
3 #include"delay.h"
4 //#include "absacc.h"
5
6 #define EEPROMPAGE 128
7 #define SST_ID 0xBF /* SST Manufacturer抯 ID code */
8 #define SST_29LE020 0x12 /* SST 29EE020 device code */
9
10 #define Base_ROM_ADD 0x4000
11 #define DATA P7 // 数据端口引脚(AD7..0)
12 #define ADDR P6 // 地址端口引脚(A15..8)
13 #define AreaSelect P4 /* 段选择,P4.0~P4.3 ; P4.5 ALE; P4.6 RD; P4.7 WR; 均为低有效*/
14 /* 其中,P4^6 // 读选通RD(低电平有效)
15 P4^7 //写选通WR(低电平有效)
16 P4^5 //地址锁存信号ALE(低电平有效)
17 */
18 void eeprom_Unlock();
19 void eeprom_Lock();
20 void SYSCLK_Init (void);
21 void delay(UINT16 ms);
22 void Enable_Chip_Data_Protection();
23 void Check_Data_Polling (UINT8 xdata *Dst, UINT8 TrueData);
24 void Check_Toggle_Ready (UINT8 xdata *Dst);
25
26
27 /******************************************************************************************************/
28 /* PROCEDURE: Check_SST_29EE020 */
29 /* */
30 /* This procedure decides whether a physical hardware device has a SST */
31 /* 29EE020 2 Mbit Page Mode EEPROM installed or not. */
32 /* */
33 /* */
34 /* Input: */
35 /* None */
36 /* */
37 /* Output: */
38 /* return -1: indicates not a SST 29EE020 */
39 /* return 0: indicates is a SST 29EE020 */
40 /*****************************************************************************************************/
41
42 int Check_SST_29EE020()
43 {
44 1 volatile UINT8 xdata *Tmp;
45 1 UINT8 SST_id1;
46 1 UINT8 SST_id2;
47 1 int ReturnStatus;
48 1
49 1 /* Issue the Software Product ID code to 29EE020 */
50 1
51 1 AreaSelect|=1;
52 1 Tmp = (UINT8 xdata *)0x5555; /* set up address to be C000:5555h */
53 1 *Tmp = 0xAA; /* write data 0xAA to the address */
54 1 AreaSelect&=~(1);
55 1 Tmp = (UINT8 xdata *)0x6AAA; /* set up address to be C000:2AAAh */
C51 COMPILER V7.06 EEPROM 12/15/2005 23:22:10 PAGE 2
56 1 *Tmp = 0x55; /* write data 0x55 to the address */
57 1 AreaSelect|=1;
58 1 Tmp = (UINT8 xdata *)0x5555; /* set up address to be C000:5555h */
59 1 *Tmp = 0x90; /* write data 0x90 to the address */
60 1
61 1 delay(10);
62 1
63 1 /* Read the product ID from 29LE020 */
64 1
65 1 AreaSelect&=~(1);
66 1 Tmp = (UINT8 xdata *)0x4000; /* set up address to be C000:0000h */
67 1 SST_id1 = *Tmp; /* get first ID byte */
68 1 Tmp = (UINT8 xdata *)0x4001; /* set up address to be C000:0001h */
69 1 SST_id2 = *Tmp;
70 1 if ((SST_id1 == SST_ID) && (SST_id2 ==SST_29LE020))
71 1 ReturnStatus = 0;
72 1 else
73 1 ReturnStatus = -1;
74 1
75 1
76 1
77 1
78 1 /* Issue the Soffware Product ID Exit code thus returning the 29EE020 */
79 1 /* to the read operating mode */
80 1
81 1 AreaSelect|=1;
82 1 Tmp = (UINT8 xdata *)0x5555; /* set up address to be C000:5555h */
83 1 *Tmp = 0xAA; /* write data 0xAA to the address */
84 1 AreaSelect&=~(1);
85 1 Tmp = (UINT8 xdata *)0x6AAA; /* set up address to be C000:2AAAh */
86 1 *Tmp = 0x55; /* write data 0x55 to the address */
87 1 AreaSelect|=1;
88 1 Tmp = (UINT8 xdata *)0x5555; /* set up address to be C000:5555h */
89 1 *Tmp =0xF0; /* write data 0xF0 to the address */
90 1
91 1 delay(10);
92 1
93 1 return(ReturnStatus);
94 1 }
95
96
97
98 /******************************************************************************************************/
99 /* PROCEDURE: Write_29EE020 */
100 /* */
101 /* This procedure can be used to write a total of 128 bytes at one write cycle to the */
102 /* SST抯 29EE020. */
103 /* */
104 /* Input: */
105 /* SRC SOURCE address containing the data which will be */
106 /* written into the 29EE020. */
107 /* Dst DESTINATION address which will be written with the */
108 /* data passed in from ds:si */
109 /* */
110 /* Output: */
111 /* None */
112 /******************************************************************************************************/
113
114 void Write_29EE020 (UINT8 blockno, UINT8 xdata *Src, UINT8 xdata *Dst)
115 {
116 1 UINT8 xdata *Temp;
117 1 UINT8 xdata *SourceBuf;
C51 COMPILER V7.06 EEPROM 12/15/2005 23:22:10 PAGE 3
118 1 UINT8 xdata *DestBuf;
119 1 int Index;
120 1
121 1 SourceBuf = Src;
122 1 DestBuf = Dst;
123 1
124 1 /************************************************************************************/
125 1 /* WRITTEN OPERATION */
126 1 /* */
127 1 /* Issue the 3-byte "enable protection" sequence followed by 128 bytes */
128 1 /* of data written to the 29EE020. */
129 1 /************************************************************************************/
130 1 AreaSelect &= 0xF0;
131 1 AreaSelect |= 1;
132 1 Temp = (UINT8 xdata *)0x5555; /* set up address to be C000:555h */
133 1 *Temp = 0xAA; /* write data 0xAA to the address */
134 1 AreaSelect &= ~1;
135 1 Temp = (UINT8 xdata *)0x6AAA; /* set up address to be C000:2AAAh */
136 1 *Temp = 0x55; /* write data 0x55 to the address */
137 1 AreaSelect |= 1;
138 1 Temp = (UINT8 xdata *)0x5555; /* set up address to be C000:5555h */
139 1 *Temp = 0xA0; /* write data 0xA0 to the address */
140 1 AreaSelect &= 0xF0;
141 1 AreaSelect|=blockno;
142 1 for (Index = 0; Index < EEPROMPAGE; Index++)
143 1 {
144 2 *DestBuf++ = *SourceBuf++; /* transfer data from source to destination */
145 2
146 2 }
147 1 delay(1); /* wait 1ms to start writing */
148 1
149 1 Check_Toggle_Ready(Dst); /* wait for TOGGLE bit to get ready */
150 1 }
151
152
153
154
155 /******************************************************************************************************/
156 /* PROCEDURE: Check_Toggle_Ready */
157 /* */
158 /* During the internal write cycle, any consecutive read operation */
159 /* on DQ6 will produce alternating 0抯 and 1抯 i.e. toggling between */
160 /* 0 and 1. When the write cycle is completed, DQ6 of the data will */
161 /* stop toggling. After the DQ6 data bit stops toggling, the device is ready */
162 /* for next operation. */
163 /* */
164 /* Input: */
165 /* Dst must already set-up by the caller */
166 /* */
167 /* Output: */
168 /* None */
169 /******************************************************************************************************/
170
171 void Check_Toggle_Ready (UINT8 xdata *Dst)
172 {
173 1 UINT8 Loop = 1;
174 1 UINT8 PreData;
175 1 UINT8 CurrData;
176 1 unsigned long TimeOut = 0;
177 1
178 1 PreData = *Dst;
179 1 PreData = PreData & 0x40;
C51 COMPILER V7.06 EEPROM 12/15/2005 23:22:10 PAGE 4
180 1 while ((TimeOut< 0x07FFFFFF) && (Loop))
181 1 {
182 2 CurrData = *Dst;
183 2 CurrData = CurrData & 0x40;
184 2 if (PreData == CurrData)
185 2 Loop = 0; /* ready to exit the while loop */
186 2 PreData = CurrData;
187 2 TimeOut++;
188 2 }
189 1 }
190
191
192
193
194 /******************************************************************************************************/
195 /* PROCEDURE: Check_Data_Polling */
196 /* */
197 /* During the internal write cycle, any attempt to read DQ7 of the last byte loaded during */
198 /* the page/byte-load cycle will receive the complement of the true data. Once the */
199 /* write cycle is completed, DQ7 will show true data. */
200 /* */
201 /* Input: */
202 /* Dst must already set-up by the caller */
203 /* True Datathis is the original (true) data */
204 /* */
205 /* Output: */
206 /* None */
207 /******************************************************************************************************/
208
209 void Check_Data_Polling (UINT8 xdata *Dst, UINT8 TrueData)
210 {
211 1 UINT8 Loop = 1;
212 1 UINT8 CurrData;
213 1 unsigned long TimeOut = 0;
214 1
215 1 TrueData = TrueData & 0x80;
216 1 while ((TimeOut< 0x07FFFFFF) && (Loop))
217 1 {
218 2 CurrData = *Dst;
219 2 CurrData = CurrData & 0x80;
220 2 if (TrueData == CurrData)
221 2 Loop = 0; /* ready to exit the while loop */
222 2 TimeOut++;
223 2 }
224 1 }
225
226
227
228
229
230 /******************************************************************************************************/
231 /* PROCEDURE: Enable_Chip_Data_Protection */
232 /* */
233 /* This procedure ENABLES the data protection feature on the 29EE020 */
234 /* 2 Mbit Page Mode EEPROM. After calling this routine, the chip cannot be written */
235 /* unless preceded by the three Byte-Load sequence. */
236 /* */
237 /* Input: */
238 /* None */
239 /* */
240 /* Output: */
241 /* None */
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