📄 ataio.h
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//********************************************************************
// ATA LOW LEVEL I/O DRIVER -- ATAIO.H (driver's public data)
//
// by Hale Landis (hlandis@ata-atapi.com)
//
// There is no copyright and there are no restrictions on the use
// of this ATA Low Level I/O Driver code. It is distributed to
// help other programmers understand how the ATA device interface
// works and it is distributed without any warranty. Use this
// code at your own risk.
//
// This code is based on the ATA-2, ATA-3 and ATA-4 standards and
// on interviews with various ATA controller and drive designers.
//
// This code has been run on many ATA (IDE) drives and
// MFM/RLL controllers. This code may be a little
// more picky about the status it sees at various times. A real
// BIOS probably would not check the status as carefully.
//
// Compile with one of the Borland C or C++ compilers.
// See the make files EXAMPLE1.MAK and EXAMPLE2.MAK.
//
// This C source file is the header file for the for this driver
// and is used in the ATAIOxxx.C files and must also be used
// by any program using this driver code.
//********************************************************************
#define ATA_DRIVER_VERSION "16M"
//**************************************************************
//
// Global defines -- ATA register and register bits.
// command block & control block regs
//
//**************************************************************
// These are the offsets into pio_reg_addrs[]
#define CB_DATA 0 // data reg in/out pio_base_addr1+0
#define CB_ERR 1 // error in pio_base_addr1+1
#define CB_FR 1 // feature reg out pio_base_addr1+1
#define CB_SC 2 // sector count in/out pio_base_addr1+2
#define CB_SN 3 // sector number in/out pio_base_addr1+3
#define CB_CL 4 // cylinder low in/out pio_base_addr1+4
#define CB_CH 5 // cylinder high in/out pio_base_addr1+5
#define CB_DH 6 // device head in/out pio_base_addr1+6
#define CB_STAT 7 // primary status in pio_base_addr1+7
#define CB_CMD 7 // command out pio_base_addr1+7
#define CB_ASTAT 8 // alternate status in pio_base_addr2+6
#define CB_DC 8 // device control out pio_base_addr2+6
#define CB_DA 9 // device address in pio_base_addr2+7
// error reg (CB_ERR) bits
#define CB_ER_ICRC 0x80 // ATA Ultra DMA bad CRC
#define CB_ER_BBK 0x80 // ATA bad block
#define CB_ER_UNC 0x40 // ATA uncorrected error
#define CB_ER_MC 0x20 // ATA media change
#define CB_ER_IDNF 0x10 // ATA id not found
#define CB_ER_MCR 0x08 // ATA media change request
#define CB_ER_ABRT 0x04 // ATA command aborted
#define CB_ER_NTK0 0x02 // ATA track 0 not found
#define CB_ER_NDAM 0x01 // ATA address mark not found
#define CB_ER_P_SNSKEY 0xf0 // ATAPI sense key (mask)
#define CB_ER_P_MCR 0x08 // ATAPI Media Change Request
#define CB_ER_P_ABRT 0x04 // ATAPI command abort
#define CB_ER_P_EOM 0x02 // ATAPI End of Media
#define CB_ER_P_ILI 0x01 // ATAPI Illegal Length Indication
// ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC)
#define CB_SC_P_TAG 0xf8 // ATAPI tag (mask)
#define CB_SC_P_REL 0x04 // ATAPI release
#define CB_SC_P_IO 0x02 // ATAPI I/O
#define CB_SC_P_CD 0x01 // ATAPI C/D
// bits 7-4 of the device/head (CB_DH) reg
#define CB_DH_LBA 0x40 // LBA bit
#define CB_DH_DEV0 0x00 // select device 0
#define CB_DH_DEV1 0x10 // select device 1
// #define CB_DH_DEV0 0xa0 // select device 0 (old definition)
// #define CB_DH_DEV1 0xb0 // select device 1 (old definition)
// status reg (CB_STAT and CB_ASTAT) bits
#define CB_STAT_BSY 0x80 // busy
#define CB_STAT_RDY 0x40 // ready
#define CB_STAT_DF 0x20 // device fault
#define CB_STAT_WFT 0x20 // write fault (old name)
#define CB_STAT_SKC 0x10 // seek complete (only SEEK command)
#define CB_STAT_SERV 0x10 // service (overlap/queued commands)
#define CB_STAT_DRQ 0x08 // data request
#define CB_STAT_CORR 0x04 // corrected (obsolete)
#define CB_STAT_IDX 0x02 // index (obsolete)
#define CB_STAT_ERR 0x01 // error (ATA)
#define CB_STAT_CHK 0x01 // check (ATAPI)
// device control reg (CB_DC) bits
#define CB_DC_HOB 0x80 // High Order Byte (48-bit LBA)
#define CB_DC_HD15 0x00 // bit 3 is reserved
// #define CB_DC_HD15 0x08 // (old definition of bit 3)
#define CB_DC_SRST 0x04 // soft reset
#define CB_DC_NIEN 0x02 // disable interrupts
// BMCR/BMIDE registers and bits
#define BM_COMMAND_REG 0 // offset to BM command reg
#define BM_CR_MASK_READ 0x00 // read from memory
#define BM_CR_MASK_WRITE 0x08 // write to memory
#define BM_CR_MASK_START 0x01 // start transfer
#define BM_CR_MASK_STOP 0x00 // stop transfer
#define BM_STATUS_REG 2 // offset to BM status reg
#define BM_SR_MASK_SIMPLEX 0x80 // simplex only
#define BM_SR_MASK_DRV1 0x40 // drive 1 can do dma
#define BM_SR_MASK_DRV0 0x20 // drive 0 can do dma
#define BM_SR_MASK_INT 0x04 // INTRQ signal asserted
#define BM_SR_MASK_ERR 0x02 // error
#define BM_SR_MASK_ACT 0x01 // active
#define BM_PRD_ADDR_LOW 4 // offset to prd addr reg low 16 bits
#define BM_PRD_ADDR_HIGH 6 // offset to prd addr reg high 16 bits
//**************************************************************
//
// Most mandtory and optional ATA commands
//
//**************************************************************
#define CMD_CFA_ERASE_SECTORS 0xC0
#define CMD_CFA_REQUEST_EXT_ERR_CODE 0x03
#define CMD_CFA_TRANSLATE_SECTOR 0x87
#define CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD
#define CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38
#define CMD_CHECK_POWER_MODE1 0xE5
#define CMD_CHECK_POWER_MODE2 0x98
#define CMD_DEVICE_RESET 0x08
#define CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90
#define CMD_FLUSH_CACHE 0xE7
#define CMD_FLUSH_CACHE_EXT 0xEA
#define CMD_FORMAT_TRACK 0x50
#define CMD_IDENTIFY_DEVICE 0xEC
#define CMD_IDENTIFY_DEVICE_PACKET 0xA1
#define CMD_IDENTIFY_PACKET_DEVICE 0xA1
#define CMD_IDLE1 0xE3
#define CMD_IDLE2 0x97
#define CMD_IDLE_IMMEDIATE1 0xE1
#define CMD_IDLE_IMMEDIATE2 0x95
#define CMD_INITIALIZE_DRIVE_PARAMETERS 0x91
#define CMD_INITIALIZE_DEVICE_PARAMETERS 0x91
#define CMD_NOP 0x00
#define CMD_PACKET 0xA0
#define CMD_READ_BUFFER 0xE4
#define CMD_READ_DMA 0xC8
#define CMD_READ_DMA_EXT 0x25
#define CMD_READ_DMA_QUEUED 0xC7
#define CMD_READ_DMA_QUEUED_EXT 0x26
#define CMD_READ_MULTIPLE 0xC4
#define CMD_READ_MULTIPLE_EXT 0x29
#define CMD_READ_SECTORS 0x20
#define CMD_READ_SECTORS_EXT 0x24
#define CMD_READ_VERIFY_SECTORS 0x40
#define CMD_READ_VERIFY_SECTORS_EXT 0x42
#define CMD_RECALIBRATE 0x10
#define CMD_SEEK 0x70
#define CMD_SET_FEATURES 0xEF
#define CMD_SET_MULTIPLE_MODE 0xC6
#define CMD_SLEEP1 0xE6
#define CMD_SLEEP2 0x99
#define CMD_SMART 0xB0
#define CMD_STANDBY1 0xE2
#define CMD_STANDBY2 0x96
#define CMD_STANDBY_IMMEDIATE1 0xE0
#define CMD_STANDBY_IMMEDIATE2 0x94
#define CMD_WRITE_BUFFER 0xE8
#define CMD_WRITE_DMA 0xCA
#define CMD_WRITE_DMA_EXT 0x35
#define CMD_WRITE_DMA_QUEUED 0xCC
#define CMD_WRITE_DMA_QUEUED_EXT 0x36
#define CMD_WRITE_MULTIPLE 0xC5
#define CMD_WRITE_MULTIPLE_EXT 0x39
#define CMD_WRITE_SECTORS 0x30
#define CMD_WRITE_SECTORS_EXT 0x34
#define CMD_WRITE_VERIFY 0x3C
#define CMD_SRST 256 // fake command code for Soft Reset
//**************************************************************
//
// Public functions in ATAIOISA.C
//
//**************************************************************
extern int dma_isa_config( int chan );
extern int dma_isa_chs( int dev, int cmd,
unsigned int fr, unsigned int sc,
unsigned int cyl, unsigned int head, unsigned int sect,
unsigned int seg, unsigned int off,
long numSect );
extern int dma_isa_lba28( int dev, int cmd,
unsigned int fr, unsigned int sc,
unsigned long lba,
unsigned int seg, unsigned int off,
long numSect );
extern int dma_isa_lba48( int dev, int cmd,
unsigned int fr, unsigned int sc,
unsigned long lbahi, unsigned long lbalo,
unsigned int seg, unsigned int off,
long numSect );
extern int dma_isa_packet( int dev,
unsigned int cpbc,
unsigned int cpseg, unsigned int cpoff,
int dir,
long dpbc,
unsigned int dpseg, unsigned int dpoff,
unsigned long lba );
//**************************************************************
//
// Public data in ATAIOINT.C
//
//**************************************************************
// Interrupt mode flag (interrupts in use if != 0 )
// This value is READ ONLY - do not change.
extern int int_use_intr_flag;
//**************************************************************
//
// Public functions in ATAIOINT.C
//
//**************************************************************
extern int int_enable_irq( int shared, int irqNum,
unsigned int bmAddr, unsigned int ataAddr );
extern void int_disable_irq( void );
//**************************************************************
//
// Public data in ATAIOPCI.C
//
//**************************************************************
extern int dma_pci_prd_type; // type of PRD list to use
#define PRD_TYPE_SIMPLE 0 // use PRD buffer, simple list
#define PRD_TYPE_COMPLEX 1 // use PRD buffer, complex list
#define PRD_TYPE_LARGE 2 // use I/O buffer, overlay I/O buffer
extern long dma_pci_largeMaxB; // max LARGE dma transfer size in bytes
extern long dma_pci_largeMaxS; // max LARGE dma transfer size in sectors
extern unsigned long far * dma_pci_largePrdBufPtr; // LARGE PRD buffer ptr
extern unsigned char far * dma_pci_largeIoBufPtr; // LARGE PRD I/O address
extern unsigned long far * dma_pci_prd_ptr; // current PRD buffer address
extern int dma_pci_num_prd; // current number of PRD entries
//**************************************************************
//
// Public functions in ATAIOPCI.C
//
//**************************************************************
extern int dma_pci_config( unsigned int regAddr );
extern void dma_pci_set_max_xfer( unsigned int seg, unsigned int off,
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