fpgapci.vhd

用vhdl编写的pci源代码。花了我2000多元钱买来的

             when cfg_rd_st3 => nxt_state1<=idle1;  
             when others => nxt_state1<=idle1;
             end case;
             case pre_state2 is 
             when idle2 => if (cfg_wr_sel='1' or io_wr_sel='1' or mem_wr_sel='1') then nxt_state2<=dev_st2;
                           else nxt_state2<=idle2;end if;
             when dev_st2 => if irdy='0' then nxt_state2<=cfg_wr_st1;
                            else nxt_state2<=dev_st2;end if;
             when cfg_wr_st1 => if irdy='0' then nxt_state2<=cfg_wr_st2;
                            else nxt_state2<=cfg_wr_st1;end if;
             when cfg_wr_st2 => if frame='0' then nxt_state2<=stop_st2;
                            else nxt_state2<=cfg_wr_st3;end if;
             when stop_st2 => nxt_state2<=cfg_wr_st3;             
             when cfg_wr_st3 => nxt_state2<=idle2;
             when others => nxt_state2<=idle2;
             end case;
             if rising_edge(clk) then trdy2<=trdy1;trdy4<=trdy3;
                                      devsel2<=devsel1;devsel4<=devsel3;
                                      stop2<=stop1;stop4<=stop3;
                                      st_clr<=st_clr1;
                                      cfgwr<=cfgwr1;
                                      data_out<=data_out1;
             end if;
             if rst='0' then basereg0<="11111111111111111111111100000001";
             elsif rising_edge(clk) then 
             if (cfgwr='1' and base0='1' and wrsel='1') then basereg0(31 downto 8)<=ad(31 downto 8);
                                               basereg0(7 downto 0)<="00000001";
             end if;end if;
             if rst='0' then basereg1<="11111111110000000000000000000000";
             elsif rising_edge(clk) then 
             if (cfgwr='1' and base1='1' and wrsel='1') then basereg1(31 downto 22)<=ad(31 downto 22);
                                               basereg1(21 downto 0)<="0000000000000000000000";
             end if;end if;             
             if rst='0' then int_reg(7 downto 1)<="0000000";
             elsif mast_en='1' then int_reg(0)<='1';
             elsif rising_edge(clk) then 
             if (cfgwr='1' and int_reg_sel='1') then int_reg(7 downto 0)<=ad(7 downto 0);
             end if;end if;
             int_reg(31 downto 8)<="000000000000000000000000";                                    
--             if rst='0' then head_reg<=(others=>'0');
             if rising_edge(clk) then if (cfgwr='1' and head_reg_sel='1') then 
             head_reg<=ad;
             elsif tranone='1' then head_reg(31 downto 2)<=head_reg(31 downto 2)+1; 
             end if;
             end if; 
--             if rst='0' then count_reg<=(others=>'0');
             if rising_edge(clk) then if (cfgwr='1' and count_reg_sel='1') then 
             count_reg<=ad;
             elsif tranone='1' then count_reg(19 downto 2)<=count_reg(19 downto 2)-1;
             end if;             
             end if; 
             if rising_edge(clk) then 
             if count_reg(19 downto 2)="000000000000000001" then mast_en<='1';
             else mast_en<='0';
             end if; end if;
             if (rst='0' or mast_en='1')then master_reg<=(others=>'0');
             elsif rising_edge(clk) then if (cfgwr='1' and master_reg_sel='1') then
             master_reg<=ad;
             end if;
             end if;
--             if rst='0' then adde_reg<=(others=>'0');
--             elsif rising_edge(clk) then if fifo_wr='1' then 
--             adde_reg<=adde_reg+ad;
--             end if;end if; 
--             if rst='0' then sub_reg<=(others=>'0');
--             elsif rising_edge(clk) then if (cfgwr='1' and sub_reg_sel='1')
--             then sub_reg<=ad;
--             elsif fifo_rd='1' then sub_reg<=sub_reg-1;
--             end if;end if;
             if rst='0' then intreg<="00000000000000000000000111111111";
             elsif rising_edge(clk) then 
             if (cfgwr='1' and int_sel='1' and wrsel='1') then intreg(31 downto 8)<="000000000000000000000001";
                                               intreg(7 downto 0)<=ad(7 downto 0);
             end if;end if;
     end process;
           par_en <='1' when pre_state1=cfg_rd_st2 else '0';
          inta<='0' when (int_reg(0)='1' and int_reg(1)='1') or (ext_inta='1' and int_reg(1)='1') else 'Z';
          cfgwr1<='1' when pre_state2=cfg_wr_st2 or pre_state2=dev_st2 or pre_state2=cfg_wr_st1 else '0';
          st_clr1<='1' when (pre_state1=dev_st1 or pre_state2=dev_st2) else '0';
          trdy1<='0' when (pre_state2=cfg_wr_st2 or pre_state1=cfg_rd_st2) 
                     else '1';
          data_out1<='1' when (pre_state1=dev_st1 or pre_state1=cfg_rd_st1 or pre_state1=cfg_rd_st2)
                        else '0';
          devsel1<='0' when (pre_state2=cfg_wr_st1 or pre_state2=dev_st2
                or pre_state1=dev_st1 or pre_state1=cfg_rd_st1 or pre_state2=cfg_wr_st2
                or pre_state1=cfg_rd_st2 or pre_state1=stop_st1 or pre_state2=stop_st2)
                     else '1';
          stop1<='0' when (pre_state1=stop_st1 or pre_state2=stop_st2) else '1';
          trdy3<='1' when (pre_state1=cfg_rd_st1 or pre_state1=cfg_rd_st2 
                          or pre_state1=cfg_rd_st3 or pre_state1=stop_st1
                          or pre_state2=cfg_wr_st1 or pre_state2=cfg_wr_st2 
                          or pre_state2=cfg_wr_st2 or pre_state2=stop_st2
                          or pre_state2=cfg_wr_st3)
                     else '0';
          devsel3<='1' when (pre_state1=cfg_rd_st1 or pre_state1=cfg_rd_st2 
                          or pre_state1=cfg_rd_st3 or pre_state1=stop_st1
                          or pre_state2=cfg_wr_st1 or pre_state2=cfg_wr_st2 
                          or pre_state2=cfg_wr_st3
                          or pre_state2=cfg_wr_st2 or pre_state2=stop_st2
                          or pre_state1=dev_st1 or pre_state2=dev_st2)
                     else '0';
 
           stop3<='1' when (pre_state1=stop_st1 or pre_state2=stop_st2
                      or pre_state1=cfg_rd_st2 or pre_state1=cfg_rd_st3
                      or pre_state2=cfg_wr_st2 or pre_state2=cfg_wr_st3) else '0';               
           trdy<=trdy2 when trdy4='1' else 'Z';
           devsel<=devsel2 when devsel4='1' else 'Z';
           stop<=stop2 when stop4='1' else 'Z';
           ad<=id when (data_out='1' and devid='1' and rdsel='1')
          else stc when (data_out='1' and statecmd='1' and rdsel='1')
          else clss when (data_out='1' and classcd='1' and rdsel='1')
          else ht when (data_out='1' and hdtp='1' and rdsel='1')
          else base when (data_out='1' and (res1='1' or res2='1' or res3='1' or res4='1' or res5='1' or base2='1' or base3='1' or base4='1' or base5='1') and rdsel='1')
          else basereg0 when (data_out='1' and base0='1' and rdsel='1')
          else basereg1 when (data_out='1' and base1='1' and rdsel='1')
          else intreg when (data_out='1' and int_sel='1' and rdsel='1')
          else int_reg when (data_out='1' and int_reg_sel='1')
          else head_reg when ((data_out='1' and head_reg_sel='1') or head_out='1') 
          else count_reg when (data_out='1' and count_reg_sel='1')
--          else adde_reg when (data_out='1' and adde_reg_sel='1')
--          else sub_reg when (data_out='1' and sub_reg_sel='1') or fifo_rd_en='1'
          else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
     state_pro : process(clk,rst)
          begin if rst='0' then pre_state1<=idle1;pre_state2<=idle2;
                elsif rising_edge(clk) then pre_state1<=nxt_state1;
                pre_state2<=nxt_state2;end if;
          end process; 
                               
     par_pro : process(clk,rst)
          begin  if rising_edge(clk) then if (par_out2='1' or fifo_rd='1' 
                 or pre_state3=add_st2 or pre_state4=add_st4)
                 then par_reg<=ad;end if;
                 end if;
                  par(0) <= par_reg(0) xor par_reg(1) xor par_reg(2) xor par_reg(3);
                  par(1) <= par_reg(4) xor par_reg(5) xor par_reg(6) xor par_reg(7);
                  par(2) <= par_reg(8) xor par_reg(9) xor par_reg(10) xor par_reg(11);
                  par(3) <= par_reg(12) xor par_reg(13) xor par_reg(14) xor par_reg(15);
                  par(4) <= par_reg(16) xor par_reg(17) xor par_reg(18) xor par_reg(19);
                  par(5) <= par_reg(20) xor par_reg(21) xor par_reg(22) xor par_reg(23);
                  par(6) <= par_reg(24) xor par_reg(25) xor par_reg(26) xor par_reg(27);
                  par(7) <= par_reg(28) xor par_reg(29) xor par_reg(30) xor par_reg(31);
                  par(8) <= par(0) xor par(1) xor par(2) xor par(3);
                  par(9) <= par(4) xor par(5) xor par(6) xor par(7);  
                  par(10) <= par(8) xor par(9);
                  par(11) <= par(10) xor cbe(3) xor cbe(2);
                  parity <= par(11) xor cbe(1) xor cbe(0) ;
           if rising_edge(clk) then par_out2<=par_en;en<=(par_out2 or fifo_rd or head_out);parity1<=parity;end if;   
            end process;
            part<=en;
            perr<='Z';
            serr<='Z';
            --led1<=mast_rd_sel;
        --    led0<=mast_wr_sel;
            --led0<=memsel;
            data_rd_out<=(data_out or data_out1) and ((iordsel and iobase0_sel) 
            or (memrdsel and membase0_sel));
            iosel<=(iordsel or iowrsel) and iobase0_sel;
            memsel<=(memrdsel or memwrsel) and membase0_sel;
            data_wr<=(cfgwr1 or cfgwr) and ((iowrsel and iobase0_sel) or 
            (memwrsel and membase0_sel));
            ext_add<=add(21 downto 0);
end beha;