fpgapci.vhd

用vhdl编写的pci源代码。花了我2000多元钱买来的

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pci is port(
clk,rst,idsel,gnt,ext_inta : in std_logic;
frame,irdy : inout std_logic;
trdy,devsel,stop,req : inout std_logic;
inta,part : out std_logic;
perr,serr : out std_logic;
--led0,led1 : out std_logic;
data_rd_out,data_wr : out std_logic;
iosel,memsel : buffer std_logic;
ext_add : out std_logic_vector(21 downto 0);
cbe : inout std_logic_vector(3 downto 0);
ad : inout std_logic_vector(31 downto 0);
fifo_rdfull,fifo_rdempty,fifo_wrempty,fifo_wrfull : in std_logic;
fifo_rd_en : buffer std_logic;
fifo_rd,fifo_wr : buffer std_logic
);
end pci;
architecture beha of pci is 
type cfg_rd_state is (idle1,dev_st1,cfg_rd_st1,cfg_rd_st2,cfg_rd_st3,stop_st1);
type cfg_wr_state is (idle2,dev_st2,cfg_wr_st1,cfg_wr_st2,cfg_wr_st3,stop_st2);
type mast_rd_state is (idle3,add_st1,add_st2,rd_trans1,rd_trans2,lasttran1,trandone);
type mast_wr_state is (idle4,add_st3,add_st4,wr_trans1,wr_trans2,lasttran3,trandone2);
signal pre_state3,nxt_state3 : mast_rd_state;
signal pre_state4,nxt_state4 : mast_wr_state;
signal pre_state1,nxt_state1 : cfg_rd_state;
signal pre_state2,nxt_state2 : cfg_wr_state;
signal mast_count_reg : std_logic_vector(7 downto 0);
signal cmd : std_logic_vector(3 downto 0);
signal add,basereg1 : std_logic_vector(31 downto 0);
signal cfg_sel,dev_sel,rdsel,wrsel,tranone,memrdsel,memwrsel : std_logic;
signal membase0_sel,mem_rd_sel,mem_wr_sel,memclr : std_logic;
signal cfg_rd_sel,cfg_wr_sel,mast_en,sub_reg_sel : std_logic;
constant id : std_logic_vector(31 downto 0) :="01000010010110000001000100000000";
constant stc : std_logic_vector(31 downto 0) :="00000100000000000000000000000111";
constant clss : std_logic_vector(31 downto 0) :="00000100000000000000000000000000";
constant ht : std_logic_vector(31 downto 0) :="00000000000000000010000000000000";
constant res : std_logic_vector(31 downto 0) :="00000000000000000000000000000000";
constant base : std_logic_vector(31 downto 0) :="00000000000000000000000000000000";
signal basereg0 : std_logic_vector(31 downto 0);
signal intreg,int_reg,head_reg,count_reg,master_reg,par_reg,adde_reg,sub_reg : std_logic_vector(31 downto 0);
signal st_clr,st_clr1,data_out1,transover1,transover2,transover3 : std_logic;
signal devid,statecmd,classcd,hdtp,base0,base1,base2,base3,base4,base5 : std_logic;
signal res1,res2,res3,res4,res5,int_sel,adde_reg_sel : std_logic;
signal trdy1,trdy2,trdy3,trdy4,devsel1,devsel2,devsel3,devsel4 : std_logic;
signal stop1,stop2,stop3,stop4,data_out,mast_rd_clr,mast_wr_clr : std_logic;
signal en,cfgwr,cfgwr1,par_out2,tranover,tranover1,head_out : std_logic;
signal transover,fifo_rd_req,fifo_wr_req,mast_rd_sel,mast_wr_sel,tranover4 : std_logic;
signal pp : std_logic_vector(6 downto 0);
signal int_reg_sel,head_reg_sel,count_reg_sel,master_reg_sel,parity,parity1 : std_logic;
signal io_sel,io_rd_sel,io_wr_sel,iordsel,iowrsel,iobase0_sel,iobase1_sel,par_en : std_logic;
signal par : std_logic_vector(11 downto 0); 
begin con_pro : process(clk,rst,st_clr,cmd,add,memclr,basereg1,basereg0,io_sel,iordsel,iobase0_sel,iowrsel,memrdsel,membase0_sel,memwrsel,
                cfg_sel,dev_sel,rdsel,wrsel,pre_state1,cfg_rd_sel,io_rd_sel,mem_rd_sel,irdy,frame,pre_state2,
                cfg_wr_sel,io_wr_sel,mem_wr_sel,mast_en,transover,mast_rd_sel,mast_wr_sel,mast_rd_clr,mast_wr_clr,
                pre_state3,tranover4,stop,trdy,devsel,pre_state4,transover3,mast_count_reg,par_reg,par,
                cbe,int_reg)
      begin  if rst='0' then add<=(others=>'0');cmd<=(others=>'0');             
             elsif rising_edge(clk) then 
             if (frame='0' and irdy='1' and trdy='1' and devsel='1')
                then cmd<=cbe;add<=ad;end if;
             end if;
             if (rst='0' or st_clr='1') then io_sel<='0';
             elsif rising_edge(clk) then 
             if (frame='0' and irdy='1' and trdy='1' and devsel='1')
             then io_sel<='1';
             else io_sel<='0';end if;
             end if;
             if cmd="0010" then iordsel<='1';
                               else iordsel<='0';
             end if;
             if cmd="0011" then iowrsel<='1';
                               else iowrsel<='0';
             end if;
             if cmd="0110" then memrdsel<='1';
                           else memrdsel<='0';
             end if;
             if cmd="0111" then memwrsel<='1';
                           else memwrsel<='0';
             end if;
             if add(31 downto 24)="11111111" then 
                                       memclr<='1';
                                      else memclr<='0';
                                      end if;
             if memclr='1' then membase0_sel<='0';
             elsif (add(31 downto 22)=basereg1(31 downto 22)) then membase0_sel<='1';
                                                           else membase0_sel<='0';
             end if;  
             if add(15 downto 8)=basereg0(15 downto 8) then iobase0_sel<='1';
                                                           else iobase0_sel<='0';
             end if;
             if io_sel='1' and iordsel='1' and iobase0_sel='1' then io_rd_sel<='1'; 
                                      else io_rd_sel<='0';
             end if;
             if io_sel='1' and iowrsel='1' and iobase0_sel='1' then io_wr_sel<='1'; 
                                      else io_wr_sel<='0';
             end if;
             if io_sel='1' and memrdsel='1' and membase0_sel='1' then mem_rd_sel<='1';
                                      else mem_rd_sel<='0';
             end if;
             if io_sel='1' and memwrsel='1' and membase0_sel='1' then mem_wr_sel<='1';
                                      else mem_wr_sel<='0';
             end if; 
             if rising_edge(clk) then 
             if (add(7 downto 2)="000001" and (iordsel='1' or iowrsel='1')) then int_reg_sel<='1';
                                             else int_reg_sel<='0';end if;
             if (add(7 downto 2)="000010" and (iordsel='1' or iowrsel='1')) then head_reg_sel<='1';
                                             else head_reg_sel<='0';end if;
             if (add(7 downto 2)="000011" and (iordsel='1' or iowrsel='1')) then count_reg_sel<='1';
                                             else count_reg_sel<='0';end if;
             if (add(7 downto 2)="000100" and (iordsel='1' or iowrsel='1')) then master_reg_sel<='1';
                                             else master_reg_sel<='0';end if; 
             if (add(7 downto 2)="000101" and (iordsel='1' or iowrsel='1')) then adde_reg_sel<='1';
                                             else adde_reg_sel<='0';end if; 
             if (add(7 downto 2)="000110" and (iordsel='1' or iowrsel='1')) then sub_reg_sel<='1';
                                             else sub_reg_sel<='0';end if;
             end if;                              
             if (rst='0' or st_clr='1') then cfg_sel<='0';
             elsif rising_edge(clk) then 
             if (idsel='1' and frame='0' and irdy='1' and trdy='1' and devsel='1')
                then cfg_sel<='1';
                else cfg_sel<='0';end if;
             end if;
             if cmd="1010" then rdsel<='1';
                           else rdsel<='0';end if;
             if cmd="1011" then wrsel<='1';
                           else wrsel<='0';end if;
             if (add(10 downto 6)="00000" and add(1 downto 0)="00") then dev_sel<='1';
                           else dev_sel<='0';end if;
             if cfg_sel='1' and dev_sel='1' and rdsel='1' then cfg_rd_sel<='1';
                           else cfg_rd_sel<='0';end if;
             if cfg_sel='1' and dev_sel='1' and wrsel='1' then cfg_wr_sel<='1';
                           else cfg_wr_sel<='0';end if;
             if rising_edge(clk) then 
             if add(5 downto 2)="0000" then devid<='1';else devid<='0';end if;
             if add(5 downto 2)="0001" then statecmd<='1';else statecmd<='0';end if;
             if add(5 downto 2)="0010" then classcd<='1';else classcd<='0';end if;
             if add(5 downto 2)="0011" then hdtp<='1';else hdtp<='0';end if;
             if add(5 downto 2)="0100" then base0<='1';else base0<='0';end if;
             if add(5 downto 2)="0101" then base1<='1';else base1<='0';end if;
             if add(5 downto 2)="0110" then base2<='1';else base2<='0';end if;
             if add(5 downto 2)="0111" then base3<='1';else base3<='0';end if;
             if add(5 downto 2)="1000" then base4<='1';else base4<='0';end if;
             if add(5 downto 2)="1001" then base5<='1';else base5<='0';end if;
             if add(5 downto 2)="1010" then res1<='1';else res1<='0';end if;
             if add(5 downto 2)="1011" then res2<='1';else res2<='0';end if;
             if add(5 downto 2)="1100" then res3<='1';else res3<='0';end if;
             if add(5 downto 2)="1101" then res4<='1';else res4<='0';end if;
             if add(5 downto 2)="1110" then res5<='1';else res5<='0';end if;
             if add(5 downto 2)="1111" then int_sel<='1';else int_sel<='0';end if;
             end if;            
             case pre_state1 is 
             when idle1 => if (cfg_rd_sel='1' or io_rd_sel='1' or mem_rd_sel='1') then nxt_state1<=dev_st1;
                           else nxt_state1<=idle1;end if;
             when dev_st1 => if irdy='0' then nxt_state1<=cfg_rd_st1;
                            else nxt_state1<=dev_st1;end if;
             when cfg_rd_st1 => if irdy='0' then nxt_state1<=cfg_rd_st2;
                            else nxt_state1<=cfg_rd_st1;end if;
             when cfg_rd_st2 => if frame='0' then nxt_state1<=stop_st1;
                            else nxt_state1<=cfg_rd_st3;end if;             
             when stop_st1 => nxt_state1<=cfg_rd_st3;