📄 mcf523x_etpu_struc.h
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vuint32_t SR3:1; /* Channel 3 Pending Service Status */
vuint32_t SR2:1; /* Channel 2 Pending Service Status */
vuint32_t SR1:1; /* Channel 1 Pending Service Status */
vuint32_t SR0:1; /* Channel 0 Pending Service Status */
} B;
} CPSSR_B;
uint32_t etpu_reserved20a[2];
union
{ /* ETPU_A Channel Service Status */
vuint32_t R;
struct
{
vuint32_t SS31:1; /* Channel 31 Service Status */
vuint32_t SS30:1; /* Channel 30 Service Status */
vuint32_t SS29:1; /* Channel 29 Service Status */
vuint32_t SS28:1; /* Channel 28 Service Status */
vuint32_t SS27:1; /* Channel 27 Service Status */
vuint32_t SS26:1; /* Channel 26 Service Status */
vuint32_t SS25:1; /* Channel 25 Service Status */
vuint32_t SS24:1; /* Channel 24 Service Status */
vuint32_t SS23:1; /* Channel 23 Service Status */
vuint32_t SS22:1; /* Channel 22 Service Status */
vuint32_t SS21:1; /* Channel 21 Service Status */
vuint32_t SS20:1; /* Channel 20 Service Status */
vuint32_t SS19:1; /* Channel 19 Service Status */
vuint32_t SS18:1; /* Channel 18 Service Status */
vuint32_t SS17:1; /* Channel 17 Service Status */
vuint32_t SS16:1; /* Channel 16 Service Status */
vuint32_t SS15:1; /* Channel 15 Service Status */
vuint32_t SS14:1; /* Channel 14 Service Status */
vuint32_t SS13:1; /* Channel 13 Service Status */
vuint32_t SS12:1; /* Channel 12 Service Status */
vuint32_t SS11:1; /* Channel 11 Service Status */
vuint32_t SS10:1; /* Channel 10 Service Status */
vuint32_t SS9:1; /* Channel 9 Service Status */
vuint32_t SS8:1; /* Channel 8 Service Status */
vuint32_t SS7:1; /* Channel 7 Service Status */
vuint32_t SS6:1; /* Channel 6 Service Status */
vuint32_t SS5:1; /* Channel 5 Service Status */
vuint32_t SS4:1; /* Channel 4 Service Status */
vuint32_t SS3:1; /* Channel 3 Service Status */
vuint32_t SS2:1; /* Channel 2 Service Status */
vuint32_t SS1:1; /* Channel 1 Service Status */
vuint32_t SS0:1; /* Channel 0 Service Status */
} B;
} CSSR_A;
union
{ /* ETPU_B Channel Service Status */
vuint32_t R;
struct
{
vuint32_t SS31:1; /* Channel 31 Service Status */
vuint32_t SS30:1; /* Channel 30 Service Status */
vuint32_t SS29:1; /* Channel 29 Service Status */
vuint32_t SS28:1; /* Channel 28 Service Status */
vuint32_t SS27:1; /* Channel 27 Service Status */
vuint32_t SS26:1; /* Channel 26 Service Status */
vuint32_t SS25:1; /* Channel 25 Service Status */
vuint32_t SS24:1; /* Channel 24 Service Status */
vuint32_t SS23:1; /* Channel 23 Service Status */
vuint32_t SS22:1; /* Channel 22 Service Status */
vuint32_t SS21:1; /* Channel 21 Service Status */
vuint32_t SS20:1; /* Channel 20 Service Status */
vuint32_t SS19:1; /* Channel 19 Service Status */
vuint32_t SS18:1; /* Channel 18 Service Status */
vuint32_t SS17:1; /* Channel 17 Service Status */
vuint32_t SS16:1; /* Channel 16 Service Status */
vuint32_t SS15:1; /* Channel 15 Service Status */
vuint32_t SS14:1; /* Channel 14 Service Status */
vuint32_t SS13:1; /* Channel 13 Service Status */
vuint32_t SS12:1; /* Channel 12 Service Status */
vuint32_t SS11:1; /* Channel 11 Service Status */
vuint32_t SS10:1; /* Channel 10 Service Status */
vuint32_t SS9:1; /* Channel 9 Service Status */
vuint32_t SS8:1; /* Channel 8 Service Status */
vuint32_t SS7:1; /* Channel 7 Service Status */
vuint32_t SS6:1; /* Channel 6 Service Status */
vuint32_t SS5:1; /* Channel 5 Service Status */
vuint32_t SS4:1; /* Channel 4 Service Status */
vuint32_t SS3:1; /* Channel 3 Service Status */
vuint32_t SS2:1; /* Channel 2 Service Status */
vuint32_t SS1:1; /* Channel 1 Service Status */
vuint32_t SS0:1; /* Channel 0 Service Status */
} B;
} CSSR_B;
uint32_t etpu_reserved23[90];
/*****************************Channels********************************/
struct
{
union
{
vuint32_t R; /* Channel Configuration Register */
struct
{
vuint32_t CIE:1; /* Channel Interruput Enable */
vuint32_t DTRE:1; /* Data Transfer Request Enable */
vuint32_t CPR:2; /* Channel Priority */
vuint32_t:3;
vuint32_t ETCS:1; /* Entry Table Condition Select */
vuint32_t:3;
vuint32_t CFS:5; /* Channel Function Select */
vuint32_t ODIS:1; /* Output disable */
vuint32_t OPOL:1; /* output polarity */
vuint32_t:3;
vuint32_t CPBA:11; /* Channel Parameter Base Address */
} B;
} CR;
union
{
vuint32_t R; /* Channel Status Control Register */
struct
{
vuint32_t CIS:1; /* Channel Interruput Status */
vuint32_t CIOS:1; /* Channel Interruput Overflow Status */
vuint32_t:6;
vuint32_t DTRS:1; /* Data Transfer Status */
vuint32_t DTROS:1; /* Data Transfer Overflow Status */
vuint32_t:6;
vuint32_t IPS:1; /* Input Pin State */
vuint32_t OPS:1; /* Output Pin State */
vuint32_t OBE:1; /* Output Buffer Enable */
vuint32_t:11;
vuint32_t FM1:1; /* Function mode */
vuint32_t FM0:1; /* Function mode */
} B;
} SCR;
union
{
vuint32_t R; /* Channel Host Service Request Register */
struct
{
vuint32_t:29; /* Host Service Request */
vuint32_t HSR:3;
} B;
} HSRR;
uint32_t etpu_reserved23;
} CHAN[127];
};
// Define instances of modules
#define ETPU (*( struct ETPU_tag *) 0x401D0000)
#define ETPU_DATA_RAM (*( uint32_t *) 0x401D8000)
#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0x401DC000)
#define ETPU_DATA_RAM_END (0x401D9800)
#define CODE_RAM (*( uint32_t *) 0x401E0000)
#ifdef __MWERKS__
#pragma pop
#endif
#ifdef __cplusplus
}
#endif
#endif /* ifdef _MCF523x_eTPU_struc_H */
/*********************************************************************
*
* Copyright:
* Freescale Semiconductor, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Freescale
* Semiconductor, Inc. This software is provided on an "AS IS"
* basis and without warranty.
*
* To the maximum extent permitted by applicable law, Freescale
* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
* AND ANY ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Freescale Semiconductor assumes no responsibility for the
* maintenance and support of this software
********************************************************************/
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