📄 mcf523x_etpu_struc.h
字号:
union
{ /* ETPU_B Channel Interruput Enable */
vuint32_t R;
struct
{
vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
} B;
} CIER_B;
uint32_t etpu_reserved17[2];
union
{ /* ETPU_A Channel Data Transfer Request Enable */
vuint32_t R;
struct
{
vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
} B;
} CDTRER_A;
union
{ /* ETPU_B Channel Data Transfer Request Enable */
vuint32_t R;
struct
{
vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
} B;
} CDTRER_B;
uint32_t etpu_reserved20[10];
union
{ /* ETPU_A Channel Pending Service Status */
vuint32_t R;
struct
{
vuint32_t SR31:1; /* Channel 31 Pending Service Status */
vuint32_t SR30:1; /* Channel 30 Pending Service Status */
vuint32_t SR29:1; /* Channel 29 Pending Service Status */
vuint32_t SR28:1; /* Channel 28 Pending Service Status */
vuint32_t SR27:1; /* Channel 27 Pending Service Status */
vuint32_t SR26:1; /* Channel 26 Pending Service Status */
vuint32_t SR25:1; /* Channel 25 Pending Service Status */
vuint32_t SR24:1; /* Channel 24 Pending Service Status */
vuint32_t SR23:1; /* Channel 23 Pending Service Status */
vuint32_t SR22:1; /* Channel 22 Pending Service Status */
vuint32_t SR21:1; /* Channel 21 Pending Service Status */
vuint32_t SR20:1; /* Channel 20 Pending Service Status */
vuint32_t SR19:1; /* Channel 19 Pending Service Status */
vuint32_t SR18:1; /* Channel 18 Pending Service Status */
vuint32_t SR17:1; /* Channel 17 Pending Service Status */
vuint32_t SR16:1; /* Channel 16 Pending Service Status */
vuint32_t SR15:1; /* Channel 15 Pending Service Status */
vuint32_t SR14:1; /* Channel 14 Pending Service Status */
vuint32_t SR13:1; /* Channel 13 Pending Service Status */
vuint32_t SR12:1; /* Channel 12 Pending Service Status */
vuint32_t SR11:1; /* Channel 11 Pending Service Status */
vuint32_t SR10:1; /* Channel 10 Pending Service Status */
vuint32_t SR9:1; /* Channel 9 Pending Service Status */
vuint32_t SR8:1; /* Channel 8 Pending Service Status */
vuint32_t SR7:1; /* Channel 7 Pending Service Status */
vuint32_t SR6:1; /* Channel 6 Pending Service Status */
vuint32_t SR5:1; /* Channel 5 Pending Service Status */
vuint32_t SR4:1; /* Channel 4 Pending Service Status */
vuint32_t SR3:1; /* Channel 3 Pending Service Status */
vuint32_t SR2:1; /* Channel 2 Pending Service Status */
vuint32_t SR1:1; /* Channel 1 Pending Service Status */
vuint32_t SR0:1; /* Channel 0 Pending Service Status */
} B;
} CPSSR_A;
union
{ /* ETPU_B Channel Pending Service Status */
vuint32_t R;
struct
{
vuint32_t SR31:1; /* Channel 31 Pending Service Status */
vuint32_t SR30:1; /* Channel 30 Pending Service Status */
vuint32_t SR29:1; /* Channel 29 Pending Service Status */
vuint32_t SR28:1; /* Channel 28 Pending Service Status */
vuint32_t SR27:1; /* Channel 27 Pending Service Status */
vuint32_t SR26:1; /* Channel 26 Pending Service Status */
vuint32_t SR25:1; /* Channel 25 Pending Service Status */
vuint32_t SR24:1; /* Channel 24 Pending Service Status */
vuint32_t SR23:1; /* Channel 23 Pending Service Status */
vuint32_t SR22:1; /* Channel 22 Pending Service Status */
vuint32_t SR21:1; /* Channel 21 Pending Service Status */
vuint32_t SR20:1; /* Channel 20 Pending Service Status */
vuint32_t SR19:1; /* Channel 19 Pending Service Status */
vuint32_t SR18:1; /* Channel 18 Pending Service Status */
vuint32_t SR17:1; /* Channel 17 Pending Service Status */
vuint32_t SR16:1; /* Channel 16 Pending Service Status */
vuint32_t SR15:1; /* Channel 15 Pending Service Status */
vuint32_t SR14:1; /* Channel 14 Pending Service Status */
vuint32_t SR13:1; /* Channel 13 Pending Service Status */
vuint32_t SR12:1; /* Channel 12 Pending Service Status */
vuint32_t SR11:1; /* Channel 11 Pending Service Status */
vuint32_t SR10:1; /* Channel 10 Pending Service Status */
vuint32_t SR9:1; /* Channel 9 Pending Service Status */
vuint32_t SR8:1; /* Channel 8 Pending Service Status */
vuint32_t SR7:1; /* Channel 7 Pending Service Status */
vuint32_t SR6:1; /* Channel 6 Pending Service Status */
vuint32_t SR5:1; /* Channel 5 Pending Service Status */
vuint32_t SR4:1; /* Channel 4 Pending Service Status */
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