📄 mcf523x_etpu_struc.h
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vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
} B;
} CIOSR_A;
union
{ /* ETPU_B Interruput Overflow Status */
vuint32_t R;
struct
{
vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
} B;
} CIOSR_B;
uint32_t etpu_reserved13[2];
union
{ /* ETPU_A Data Transfer Overflow Status */
vuint32_t R;
struct
{
vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
} B;
} CDTROSR_A;
union
{ /* ETPU_B Data Transfer Overflow Status */
vuint32_t R;
struct
{
vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
} B;
} CDTROSR_B;
uint32_t etpu_reserved15[2];
union
{ /* ETPU_A Channel Interruput Enable */
vuint32_t R;
struct
{
vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
} B;
} CIER_A;
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