📄 mcf523x_etpu_struc.h
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union
{ /* ETPU_B TCR2 Visibility Register */
vuint32_t R;
} TB2R_B;
union
{ /* ETPU_B STAC Configuration Register */
vuint32_t R;
struct
{
vuint32_t REN1:1; /* Resource Enable TCR1 */
vuint32_t RSC1:1; /* Resource Control TCR1 */
vuint32_t VALID1:1; /* TCR1 Server Valid */
vuint32_t:9;
vuint32_t SRV1:4; /* Resource Server Slot */
vuint32_t REN2:1; /* Resource Enable TCR2 */
vuint32_t RSC2:1; /* Resource Control TCR2 */
vuint32_t VALID2:1; /* TCR2 Server Valid */
vuint32_t:9;
vuint32_t SRV2:4; /* Resource Server Slot */
} B;
} REDCR_B;
uint32_t etpu_reserved7[108];
/*****************************Status and Control Registers**************************/
union
{ /* ETPU_A Channel Interrut Status */
vuint32_t R;
struct
{
vuint32_t CIS31:1; /* Channel 31 Interrut Status */
vuint32_t CIS30:1; /* Channel 30 Interrut Status */
vuint32_t CIS29:1; /* Channel 29 Interrut Status */
vuint32_t CIS28:1; /* Channel 28 Interrut Status */
vuint32_t CIS27:1; /* Channel 27 Interrut Status */
vuint32_t CIS26:1; /* Channel 26 Interrut Status */
vuint32_t CIS25:1; /* Channel 25 Interrut Status */
vuint32_t CIS24:1; /* Channel 24 Interrut Status */
vuint32_t CIS23:1; /* Channel 23 Interrut Status */
vuint32_t CIS22:1; /* Channel 22 Interrut Status */
vuint32_t CIS21:1; /* Channel 21 Interrut Status */
vuint32_t CIS20:1; /* Channel 20 Interrut Status */
vuint32_t CIS19:1; /* Channel 19 Interrut Status */
vuint32_t CIS18:1; /* Channel 18 Interrut Status */
vuint32_t CIS17:1; /* Channel 17 Interrut Status */
vuint32_t CIS16:1; /* Channel 16 Interrut Status */
vuint32_t CIS15:1; /* Channel 15 Interrut Status */
vuint32_t CIS14:1; /* Channel 14 Interrut Status */
vuint32_t CIS13:1; /* Channel 13 Interrut Status */
vuint32_t CIS12:1; /* Channel 12 Interrut Status */
vuint32_t CIS11:1; /* Channel 11 Interrut Status */
vuint32_t CIS10:1; /* Channel 10 Interrut Status */
vuint32_t CIS9:1; /* Channel 9 Interrut Status */
vuint32_t CIS8:1; /* Channel 8 Interrut Status */
vuint32_t CIS7:1; /* Channel 7 Interrut Status */
vuint32_t CIS6:1; /* Channel 6 Interrut Status */
vuint32_t CIS5:1; /* Channel 5 Interrut Status */
vuint32_t CIS4:1; /* Channel 4 Interrut Status */
vuint32_t CIS3:1; /* Channel 3 Interrut Status */
vuint32_t CIS2:1; /* Channel 2 Interrut Status */
vuint32_t CIS1:1; /* Channel 1 Interrut Status */
vuint32_t CIS0:1; /* Channel 0 Interrut Status */
} B;
} CISR_A;
union
{ /* ETPU_B Channel Interruput Status */
vuint32_t R;
struct
{
vuint32_t CIS31:1; /* Channel 31 Interrut Status */
vuint32_t CIS30:1; /* Channel 30 Interrut Status */
vuint32_t CIS29:1; /* Channel 29 Interrut Status */
vuint32_t CIS28:1; /* Channel 28 Interrut Status */
vuint32_t CIS27:1; /* Channel 27 Interrut Status */
vuint32_t CIS26:1; /* Channel 26 Interrut Status */
vuint32_t CIS25:1; /* Channel 25 Interrut Status */
vuint32_t CIS24:1; /* Channel 24 Interrut Status */
vuint32_t CIS23:1; /* Channel 23 Interrut Status */
vuint32_t CIS22:1; /* Channel 22 Interrut Status */
vuint32_t CIS21:1; /* Channel 21 Interrut Status */
vuint32_t CIS20:1; /* Channel 20 Interrut Status */
vuint32_t CIS19:1; /* Channel 19 Interrut Status */
vuint32_t CIS18:1; /* Channel 18 Interrut Status */
vuint32_t CIS17:1; /* Channel 17 Interrut Status */
vuint32_t CIS16:1; /* Channel 16 Interrut Status */
vuint32_t CIS15:1; /* Channel 15 Interrut Status */
vuint32_t CIS14:1; /* Channel 14 Interrut Status */
vuint32_t CIS13:1; /* Channel 13 Interrut Status */
vuint32_t CIS12:1; /* Channel 12 Interrut Status */
vuint32_t CIS11:1; /* Channel 11 Interrut Status */
vuint32_t CIS10:1; /* Channel 10 Interrut Status */
vuint32_t CIS9:1; /* Channel 9 Interrut Status */
vuint32_t CIS8:1; /* Channel 8 Interrut Status */
vuint32_t CIS7:1; /* Channel 7 Interrut Status */
vuint32_t CIS6:1; /* Channel 6 Interrut Status */
vuint32_t CIS5:1; /* Channel 5 Interrut Status */
vuint32_t CIS4:1; /* Channel 4 Interrut Status */
vuint32_t CIS3:1; /* Channel 3 Interrut Status */
vuint32_t CIS2:1; /* Channel 2 Interrut Status */
vuint32_t CIS1:1; /* Channel 1 Interrupt Status */
vuint32_t CIS0:1; /* Channel 0 Interrupt Status */
} B;
} CISR_B;
uint32_t etpu_reserved9[2];
union
{ /* ETPU_A Data Transfer Request Status */
vuint32_t R;
struct
{
vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
} B;
} CDTRSR_A;
union
{ /* ETPU_B Data Transfer Request Status */
vuint32_t R;
struct
{
vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
} B;
} CDTRSR_B;
uint32_t etpu_reserved11[2];
union
{ /* ETPU_A Interruput Overflow Status */
vuint32_t R;
struct
{
vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
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