omap-tsc2101.c

Linux Kernel 2.6.9 for OMAP1710

/*
 *  linux/sound/arm/omap-tsc2101.c
 *
 *  Copyright (C) 2003-2004 Russell King.
 *  Copyright (C) 2004  Texas Instruments Inc
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * History:
 *
 * 04-23-2004   Kshitij         Changes for omap24xx/tsc2101
 *
 *
 *
 */


/********** linux/sound/arm/omap-tsc2101.c *************/
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <asm/arch/eac.h>
#include <sound/driver.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/delay.h>
#include <asm/arch/bus.h>

#include "omap_pcm.h"
#include "tsc_2101.h"
#ifdef TEST_PLAY
#include "wavefile.h"
#endif

#undef TEST
//#define TEST
#ifdef TEST
#define DPRINTK(fmt, args...) printk(KERN_INFO "\n %s: %s:  " fmt,__FILE__,__FUNCTION__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif

//#define CONFIG_PM 

//#define TEST_PLAY
#undef TEST_PLAY

static int ret;
int retval;
u16 tmp;
/*
struct omap_samplerate_info{
	unsigned int fs;
	unsigned int clkdiv;
	u16 divisor;
      	u16 fs_44kHz;
	u16 pll0;
	u16 pll1;
}; */
struct omap_snd_ops {
	const char *name;
	int	(*startup)(struct device *dev);
	void	(*shutdown)(struct device *dev);
	int	(*setruntime)(struct device *dev, snd_pcm_runtime_t *runtime);
	int	(*samplerate)(struct device *dev, unsigned int rate, struct omap_samplerate_info *sr);
	void	(*suspend)(struct device *dev);
	void	(*resume)(struct device *dev);
};

extern u16 omap1610_uwire_data_transfer(u8 cs, u16 data, u8 trans_size, u8 rec_size);

/*----------The  McBSP specific functions-------------------*/

static int McBSP_Init(struct device *dev)
{
	DPRINTK("McBSP_INIT()");
	return 0;
}

static void McBSP_shutdown(struct device *dev)
{
}

static int McBSP_samplerate(struct device *dev, unsigned int rate, struct omap_samplerate_info *sr)
{
	DPRINTK("configure samplerate at McBsp done");
	return 0;
}
static int McBSP_setruntime(struct device *dev, snd_pcm_runtime_t *runtime)
{
	runtime->hw.rate_max = 48000;
	runtime->hw.rate_min = 8000;
	return 0;
}

static void McBSP_suspend(struct device *dev)
{
}

static void McBSP_resume(struct device *dev)
{
}



static struct omap_snd_ops McBSP_ops = {
	.name		= "McBSP",
	.startup	= McBSP_Init,
	.shutdown	= McBSP_shutdown,
	.setruntime	= McBSP_setruntime,
	.samplerate	= McBSP_samplerate,
	.suspend	= McBSP_suspend,
	.resume		= McBSP_resume,
};
/*--------------------End --McBSP specific functions--------------------*/

/*----------The  eac specific functions-------------------*/

static int eac_init(struct device *dev)
{
	 DPRINTK("EAC_INIT");
	/* Software reset to gets things into a predefined state...*/
	writew(0x2, OMAP24XX_EAC_SYSCONFIG);


	/* EAC module power on */
	//writew(0x0,OMAP24XX_EAC_AGCTR);
	writew(0x8 | 0x2,OMAP24XX_EAC_AGCTR);
	eac_configure(dev);
	return 0;
}


static int eac_setruntime(struct device *dev, snd_pcm_runtime_t *runtime)
{
	 DPRINTK("EAC_SETRUNTIME");
	runtime->hw.rate_max = 48000;
	runtime->hw.rate_min = 8000;
	return 0;
}

static int eac_shutdown(struct device *dev)
{	 
	 DPRINTK("EAC_SHUTDOWN");
	/* EAC module power off */
	writew(0x1,OMAP24XX_EAC_AGCTR);
	return 0;
}


static void audio_dma_callback(int lch, u16 ch_status, void *data)
{
	DPRINTK("\n inside audio dma callback");
}	


#ifdef TEST_PLAY	
/* test play routine to play a wave file */
void test_play(struct device *dev)
{
#define EAC_PHY_BASE_ADDR           0x48090000
#define SYSCONFIG_OFFSET        0x82
#define AGCTR_OFFSET            0x60
#define MPMCCFR_OFFSET          0x22
#define MPCTR_OFFSET            0x20
#define BPCTR_OFFSET            0x30
#define CPTCTL_OFFSET           0x8
#define AMSCFR_OFFSET           0x40
#define AGCFR_OFFSET            0x5E
#define ADRDR_OFFSET            0x5C
#define AMVCTR_OFFSET           0x42
#define AGCFR3_OFFSET           0x64

#define dev_name "eac"

        //volatile unsigned short *ADRDR = (volatile unsigned short *)(EAC_BASE_ADDR+ADRDR_OFFSET);
        int dev_id = 10;
        int ch1;
        int cnt = 0;
	int SizeOfBlock;
	int NoOfBlocks;
        dma_channel_params params;
        struct omap_samplerate_info sr;

#if 1
	volatile unsigned short *SYSCONFIG = (volatile unsigned short *)(EAC_BASE_ADDR+SYSCONFIG_OFFSET);
	volatile unsigned short *AGCTR = (volatile unsigned short *)(EAC_BASE_ADDR+AGCTR_OFFSET);
	volatile unsigned short *MPMCCFR = (volatile unsigned short *)(EAC_BASE_ADDR+MPMCCFR_OFFSET);
	volatile unsigned short *MPCTR = (volatile unsigned short *)(EAC_BASE_ADDR+MPCTR_OFFSET);
	volatile unsigned short *BPCTR = (volatile unsigned short *)(EAC_BASE_ADDR+BPCTR_OFFSET);
	volatile unsigned short *CPTCTL = (volatile unsigned short *)(EAC_BASE_ADDR+CPTCTL_OFFSET);
	volatile unsigned short *AMSCFR = (volatile unsigned short *)(EAC_BASE_ADDR+AMSCFR_OFFSET);
	volatile unsigned short *AGCFR = (volatile unsigned short *)(EAC_BASE_ADDR+AGCFR_OFFSET);
        volatile unsigned short *AGCFR3 = (volatile unsigned short *)(EAC_BASE_ADDR+AGCFR3_OFFSET);	
	volatile unsigned short *ADRDR = (volatile unsigned short *)(EAC_BASE_ADDR+ADRDR_OFFSET);
	volatile unsigned short *AMVCTR = (volatile unsigned short *)(EAC_BASE_ADDR+AMVCTR_OFFSET);

	// McSPI Registers
	volatile unsigned int *pMCSPI_Revision =	(volatile unsigned int *)	(0xc2804000 + 0x0);
	volatile unsigned int *pMCSPI_SysConfig =	(volatile unsigned int *)	(0xc2804000 + 0x10);
	volatile unsigned int *pMCSPI_SysStatus = 	(volatile unsigned int *)	(0xc2804000 + 0x14);
	volatile unsigned int *pMCSPI_IrqStatus = 	(volatile unsigned int *)	(0xc2804000 + 0x18);	
	volatile unsigned int *pMCSPI_IrqEnable =	(volatile unsigned int *)	(0xc2804000 + 0x1C);
	volatile unsigned int *pMCSPI_Syst =		(volatile unsigned int *)	(0xc2804000 + 0x24);
	volatile unsigned int *pMCSPI_ModCtrl = 	(volatile unsigned int *)	(0xc2804000 + 0x28);
	volatile unsigned int *pMCSPI_Ch0Config = 	(volatile unsigned int *)	(0xc2804000 + 0x2C);
	volatile unsigned int *pMCSPI_Ch0Stat =		(volatile unsigned int *)	(0xc2804000 + 0x30);
	volatile unsigned int *pMCSPI_Ch0Ctrl =		(volatile unsigned int *)	(0xc2804000 + 0x34);
	volatile unsigned int *pMCSPI_Tx0 =		(volatile unsigned int *)	(0xc2804000 + 0x38);
	volatile unsigned int *pMCSPI_Rx0 = 		(volatile unsigned int *)	(0xc2804000 + 0x3C);
#endif
	int i;
	int wav_phys;


	eac_samplerate(dev, 44100, &sr);

#if 0
/******************************************************************
	 * The TSC2101 is configured through the McSPI device.
	 */
	
		// Configure MCSPI Device:			
	*pMCSPI_IrqEnable = 0x0;			// MCSPI_IRQENABLE - Don't enable any Interrupts at this stage.
	
	*pMCSPI_ModCtrl = 0x0;				// MCSPI_MODULCTRL - Put into Master Mode (Reset is Slave).
	
	*pMCSPI_Ch0Config = 0x000607C0;		// MCSPI_CHCONF0 - Set CS Active Low, Set Word Size to 16-Bits
	
	*pMCSPI_Ch0Ctrl = 0x1;				// MCSPI_CHCTRL0 - Enable Channel 0				
			
	*pMCSPI_Tx0 = 0x1000;				// MCSPI_TX0 - Write Command Word = Write Page 2 From 0x0 Addr
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 1 Reg of Page 2
	*pMCSPI_Tx0 = 0x7;					// Set DAC & ADC Sample Rate to 48kHz 			
										
	// MCSPI_TX0 - Write 0x0 to Gain Ctrl HeadSet/Aux I/P Reg of Page 2									
	*pMCSPI_Tx0 = 0x0;					// Not configured at this stage
	
	// MCSPI_TX0 - Write 0x0000 to Codec DAC Gain Ctrl Reg of Page 2	
	*pMCSPI_Tx0 = 0x4040;			// Set Left & Right Channels to Half Volume
	
	// MCSPI_TX0 - Write 0x0 to Mixer PGA Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Not configured at this stage
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 2 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Not configured at this stage
	
	// MCSPI_TX0 - Write 0x0 to Codec Power Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// All Sources Powered Up
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 3 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Fsref is 48kHz, Left & Right Volume Ctrls are independent
		
	for (i = 0; i < 20; i++)
	{
		// Audio Bass Boost Coefficients - Not Implemeted		
		*pMCSPI_Tx0 = 0x0;				// Not configured at this stage
	}
	
	// MCSPI_TX0 - Write 0x0 to PLL Programmability 1 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to PLL Programmability 2 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented

	// MCSPI_TX0 - Write 0xF8 to Audio Ctrl 4 Reg of Page 2
	*pMCSPI_Tx0 = 0xF8;				// Disable all Soft-Stepping
	
	// MCSPI_TX0 - Write 0x0 to Gain Ctrl Handset I/P Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Not configured at this stage
	
	// MCSPI_TX0 - Write 0x0 to Gain Ctrl Cell Phone I/P & Buzzer I/P Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Not configured at this stage
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 5 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 6 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to Audio Ctrl 7 Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented

	// MCSPI_TX0 - Write 0x0 to GPIO Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to AGC Cell Phone I/P Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to Driver Power Down Status Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to Mic AGC Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	// MCSPI_TX0 - Write 0x0 to Cell Phone AGC Ctrl Reg of Page 2
	*pMCSPI_Tx0 = 0x0;					// Register Not Implemented
	
	*pMCSPI_Ch0Ctrl = 0x0;				// MCSPI_CHCTRL0 - Disable Channel 0

#endif 
#if 0
	// Software reset to gets things into a predefined state...
	//*SYSCONFIG = 2;
	
	//pAGCTR->reg.MCLK_EN and AUDEN set to 1... + enable read DMA
	//*AGCTR |= 0x8|0x2;
	
	
	//*MPMCCFR |= 0x200; // Enable mu-Law expanding on MD port.
	
	//Enabling CODEC and MD & BT ports.
	// NOTE: enabling these ports will deny access to certain registers (i.e. MPMCCFR)
	//*MPCTR |= 0x81; // CKEN and MC_EN
	//*BPCTR |= 0x81; // CKEN and MC_EN
	//*CPTCTL |= 0x8; // CPEN
	
	//*AMSCFR |= (1<<6); // Activate K7
	//*AMSCFR |= (1<<7); // Activate K8
	//*AMSCFR |= (1<<1); // Activate K2
	//*AMSCFR |= (1<<0); // Activate K1
	
	//*AMSCFR = 0x11;

	// Set up for wavData format...
	//*AGCFR |= 0x6C0; // 44100/16/2
	*AGCFR |= 0x600;
	*AGCFR3 |= 0xA3 | (0x6 << 9);	
	// Reduce DMA volume.
	//*AMVCTR = ~0xFF; // Clear
	//*AMVCTR |= 0xFF&219;
#endif
	wav_phys = __virt_to_phys((int)wavData);

         ret = omap_request_dma(dev_id,dev_name,(audio_dma_callback), NULL, &ch1);
        printk("\n dma channel allocated ch1= %d", ch1);

        params.data_type = 0x1; /* data type 16 */
        params.elem_count = 32;
        params.frame_count = 16;

        params.src_amode = 1; /* post increment */
        params.src_start = (unsigned int)wav_phys;
        params.src_ei= 0;
        params.src_fi = 0;

        params.dst_amode = 0;
        params.dst_start = EAC_PHY_BASE_ADDR + ADRDR_OFFSET;
        params.dst_ei = 0;
        params.dst_fi = 0;         /* source frame index */

        params.trigger = 18;
        params.sync_mode = 0x1; /* block synch */
        params.src_or_dst_synch = 0x1;
        omap_set_dma_params(ch1, params);
	
	SizeOfBlock = params.elem_count*params.frame_count*2; // 16-bit per element.
	NoOfBlocks = lengthData/SizeOfBlock;
	*AGCTR |= 0x1000;
	while(1)
        {
                int val;
                omap_start_dma(ch1);
                cnt++;
                if (cnt > NoOfBlocks)
                {
                        // Return to beginning of wave file.
                        params.src_start                        = (unsigned int)wav_phys; // The wave file.
                        params.src_amode                        = 0x1;
                        cnt=0;
                }
                else
                {
                        params.src_start                        = ((unsigned int)wav_phys)+SizeOfBlock*cnt;
                        params.src_amode                        = 0x1;
                }

                val = readl(OMAP_DMA4_CCR_REG(ch1));
                // Wait until transfer is complete.
                while ( (val & 0x80) != 0)
			val = readl(OMAP_DMA4_CCR_REG(ch1));

		//DPRINTK("\n dma block transfer end cnt = %d", cnt);
                // Call the DMA class's setup channel function
                omap_set_dma_params(ch1, params);
        }
	cnt =0;
}
#endif

/* configure the eac codec serial port*/
static int eac_configure(struct device *dev)
{

	 DPRINTK("EAC_CONFIGURE");

#if 0	
	/* configure the codec serial porst as */
	/* PCM mode / 2 time slots per frame */
	writew(0x9,OMAP24XX_EAC_CPCFR1);

	/*
	serial clock cycles for time slot 0 same as other time slots : TSOL = 0X0
	16 data bits per audio time slot: BPTSL = 0X1 (only the 16 MBSs are used)
	32 serial clock (BCLK) cycles for all time slots except time slot 0: TSLL = 0X5
	*/
	writew(0xD,OMAP24XX_EAC_CPCFR2);

	/*
	No BIT_CLK cycle delay of the serial data output and input signals in the reference to the leading edge of the SYNC signal: DDLY = 0x0
	Data serial output is enable during the audio frame are not valid: TRSEN = 0X1
	The CSYNC signal will be generated with the negative edge of the CSCLK signal. Also the CDATO signal will be 
	generated with the negative edge of the CSCLK signal and the CDATI signal will be sampled with the positive edge of the CSCLK signal: CLKBP = 0X1
	The polarity of the CODEC port interface frame sync (CSYNC) output signal is active high for time slot 0: CSYNCP = 0x1 (Time slot 0 : left sample)
	The length of the CODEC port interface frame sync (CSYNC) output signal is the same number of CSCLK cycles as time slot 0: CSYNCL = 0X1
	The direction of the CODEC port interface serial clock (CP_SCLK) signal is an output of the device: CSCLKD = 0x0
	The direction of the CODEC port interface frame sync (CP_SYNC) signal is an output from the device: CSYNCD = 0
	*/
	writew(0x78,OMAP24XX_EAC_CPCFR3);

	/*
	Not address / data time slot: ATSL = 0X0