reg_booke.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 452 行 · 第 1/2 页
H
452 行
/* * Contains register definitions common to the Book E PowerPC * specification. Notice that while the IBM-40x series of CPUs * are not true Book E PowerPCs, they borrowed a number of features * before Book E was finalized, and are included here as well. Unfortunatly, * they sometimes used different locations than true Book E CPUs did. */#ifdef __KERNEL__#ifndef __ASM_PPC_REG_BOOKE_H__#define __ASM_PPC_REG_BOOKE_H__#ifndef __ASSEMBLY__/* Device Control Registers */void __mtdcr(int reg, unsigned int val);unsigned int __mfdcr(int reg);#define mfdcr(rn) \ ({unsigned int rval; \ if (__builtin_constant_p(rn)) \ asm volatile("mfdcr %0," __stringify(rn) \ : "=r" (rval)); \ else \ rval = __mfdcr(rn); \ rval;})#define mtdcr(rn, v) \do { \ if (__builtin_constant_p(rn)) \ asm volatile("mtdcr " __stringify(rn) ",%0" \ : : "r" (v)); \ else \ __mtdcr(rn, v); \} while (0)/* R/W of indirect DCRs make use of standard naming conventions for DCRs */#define mfdcri(base, reg) \({ \ mtdcr(base ## _CFGADDR, base ## _ ## reg); \ mfdcr(base ## _CFGDATA); \})#define mtdcri(base, reg, data) \do { \ mtdcr(base ## _CFGADDR, base ## _ ## reg); \ mtdcr(base ## _CFGDATA, data); \} while (0)/* Performance Monitor Registers */#define mfpmr(rn) ({unsigned int rval; \ asm volatile("mfpmr %0," __stringify(rn) \ : "=r" (rval)); rval;})#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))#endif /* __ASSEMBLY__ *//* Machine State Register (MSR) Fields */#define MSR_UCLE (1<<26) /* User-mode cache lock enable */#define MSR_SPE (1<<25) /* Enable SPE */#define MSR_DWE (1<<10) /* Debug Wait Enable */#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */#define MSR_IS MSR_IR /* Instruction Space */#define MSR_DS MSR_DR /* Data Space */#define MSR_PMM (1<<2) /* Performance monitor mark bit *//* Default MSR for kernel mode. */#if defined (CONFIG_40x)#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE|MSR_DE)#elif defined(CONFIG_BOOKE)#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE)#endif/* Special Purpose Registers (SPRNs)*/#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */#define SPRN_MCSR 0x23C /* Machine Check Status Register */#define SPRN_MCAR 0x23D /* Machine Check Address Register */#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */#define SPRN_PID1 0x279 /* Process ID Register 1 */#define SPRN_PID2 0x27A /* Process ID Register 2 */#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */#define SPRN_MMUCR 0x3B2 /* MMU Control Register */#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */#define SPRN_SGR 0x3B9 /* Storage Guarded Register */#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */#define SPRN_SLER 0x3BB /* Little-endian real mode */#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */#define SPRN_PIT 0x3DB /* Programmable Interval Timer */#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */#define SPRN_SVR 0x3FF /* System Version Register *//* * SPRs which have conflicting definitions on true Book E versus classic, * or IBM 40x. */#ifdef CONFIG_BOOKE#define SPRN_PID 0x030 /* Process ID */#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */#define SPRN_DEAR 0x03D /* Data Error Address Register */#define SPRN_ESR 0x03E /* Exception Syndrome Register */#define SPRN_PIR 0x11E /* Processor Identification Register */#define SPRN_DBSR 0x130 /* Debug Status Register */#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */#define SPRN_DAC1 0x13C /* Data Address Compare 1 */#define SPRN_DAC2 0x13D /* Data Address Compare 2 */#define SPRN_TSR 0x150 /* Timer Status Register */#define SPRN_TCR 0x154 /* Timer Control Register */#endif /* Book E */#ifdef CONFIG_40x#define SPRN_PID 0x3B1 /* Process ID */#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */#define SPRN_DEAR 0x3D5 /* Data Error Address Register */#define SPRN_TSR 0x3D8 /* Timer Status Register */#define SPRN_TCR 0x3DA /* Timer Control Register */#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */#define SPRN_DBSR 0x3F0 /* Debug Status Register */ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */#endif/* Bit definitions for CCR1. */#define CCR1_TCS 0x00000080 /* Timer Clock Select *//* Bit definitions for the MCSR. */#ifdef CONFIG_440A#define MCSR_MCS 0x80000000 /* Machine Check Summary */#define MCSR_IB 0x40000000 /* Instruction PLB Error */#define MCSR_DRB 0x20000000 /* Data Read PLB Error */#define MCSR_DWB 0x10000000 /* Data Write PLB Error */#define MCSR_TLBP 0x08000000 /* TLB Parity Error */#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */#endif#ifdef CONFIG_E500#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */#endif/* Bit definitions for the DBSR. *//* * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. */#ifdef CONFIG_BOOKE#define DBSR_IC 0x08000000 /* Instruction Completion */#define DBSR_BT 0x04000000 /* Branch Taken */#define DBSR_TIE 0x01000000 /* Trap Instruction Event */#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */⌨️ 快捷键说明
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