gt64260_defs.h
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#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64#define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74#define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84#define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94#define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4#define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4#define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4#define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4#define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4#define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4#define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8/* PCI Snoop Control Registers */#define GT64260_PCI_SNOOP_WINDOWS 4#define GT64260_PCI_SNOOP_NONE 0x00000000#define GT64260_PCI_SNOOP_WT 0x00001000#define GT64260_PCI_SNOOP_WB 0x00002000#define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00#define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04#define GT64260_PCI_0_SNOOP_0_TOP 0x1f08#define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10#define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14#define GT64260_PCI_0_SNOOP_1_TOP 0x1f18#define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20#define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24#define GT64260_PCI_0_SNOOP_2_TOP 0x1f28#define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30#define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34#define GT64260_PCI_0_SNOOP_3_TOP 0x1f38#define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80#define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84#define GT64260_PCI_1_SNOOP_0_TOP 0x1f88#define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90#define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94#define GT64260_PCI_1_SNOOP_1_TOP 0x1f98#define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0#define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4#define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8#define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0#define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4#define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8/* PCI Error Report Registers */#define GT64260_PCI_0_ERR_SERR_MASK 0x0c28#define GT64260_PCI_0_ERR_ADDR_LO 0x1d40#define GT64260_PCI_0_ERR_ADDR_HI 0x1d44#define GT64260_PCI_0_ERR_DATA_LO 0x1d48#define GT64260_PCI_0_ERR_DATA_HI 0x1d4c#define GT64260_PCI_0_ERR_CMD 0x1d50#define GT64260_PCI_0_ERR_CAUSE 0x1d58#define GT64260_PCI_0_ERR_MASK 0x1d5c#define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8#define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0#define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4#define GT64260_PCI_1_ERR_DATA_LO 0x1dc8#define GT64260_PCI_1_ERR_DATA_HI 0x1dcc#define GT64260_PCI_1_ERR_CMD 0x1dd0#define GT64260_PCI_1_ERR_CAUSE 0x1dd8#define GT64260_PCI_1_ERR_MASK 0x1ddc/* PCI Slave Address Decoding Registers */#define GT64260_PCI_SCS_WINDOWS 4#define GT64260_PCI_CS_WINDOWS 4#define GT64260_PCI_BOOT_WINDOWS 1#define GT64260_PCI_P2P_MEM_WINDOWS 2#define GT64260_PCI_P2P_IO_WINDOWS 1#define GT64260_PCI_DAC_SCS_WINDOWS 4#define GT64260_PCI_DAC_CS_WINDOWS 4#define GT64260_PCI_DAC_BOOT_WINDOWS 1#define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2#define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08#define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08#define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c#define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c#define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10#define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10#define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18#define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14#define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24#define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25)#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26)#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c#define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48#define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48#define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c#define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c#define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50#define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50#define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58#define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54#define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c#define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c#define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88#define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88#define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c#define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c#define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90#define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90#define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98#define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94#define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4#define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc#define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8#define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8#define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc#define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc#define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0#define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0#define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8#define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4#define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec#define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc/* ***************************************************************************** * * I2O Controller Interface Registers * ***************************************************************************** *//* FIXME: fill in *//* ***************************************************************************** * * DMA Controller Interface Registers * ***************************************************************************** *//* FIXME: fill in *//* ***************************************************************************** * * Timer/Counter Interface Registers * ***************************************************************************** *//* FIXME: fill in *//* ***************************************************************************** * * Communications Controller (Enet, Serial, etc.) Interface Registers * ***************************************************************************** */#define GT64260_ENET_0_CNTL_LO 0xf200#define GT64260_ENET_0_CNTL_HI 0xf204#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c#define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210#define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218#define GT64260_ENET_1_CNTL_LO 0xf220#define GT64260_ENET_1_CNTL_HI 0xf224#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c#define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230#define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238#define GT64260_ENET_2_CNTL_LO 0xf240#define GT64260_ENET_2_CNTL_HI 0xf244#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c#define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250#define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258#define GT64260_MPSC_0_CNTL_LO 0xf280#define GT64260_MPSC_0_CNTL_HI 0xf284#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c#define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290#define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294#define GT64260_MPSC_1_CNTL_LO 0xf2c0#define GT64260_MPSC_1_CNTL_HI 0xf2c4#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc#define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0#define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320#define GT64260_SER_INIT_LAST_DATA 0xf324#define GT64260_SER_INIT_CONTROL 0xf328#define GT64260_SER_INIT_STATUS 0xf32c#define GT64260_COMM_ARBITER_CNTL 0xf300#define GT64260_COMM_CONFIG 0xb40c#define GT64260_COMM_XBAR_TO 0xf304
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