ibm403.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 480 行 · 第 1/2 页

/*
 * Authors: Armin Kuster <[e-mail]> and Tom Rini <[e-mail]>
 *
 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */


#ifdef __KERNEL__
#ifndef __ASM_IBM403_H__
#define __ASM_IBM403_H__

#include <linux/config.h>

#if defined(CONFIG_403GCX)

#define	DCRN_BE_BASE		0x090
#define	DCRN_DMA0_BASE		0x0C0
#define	DCRN_DMA1_BASE		0x0C8
#define	DCRN_DMA2_BASE		0x0D0
#define	DCRN_DMA3_BASE		0x0D8
#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
#define	DCRN_DMASR_BASE		0x0E0

#define	DCRN_EXIER_BASE		0x042
#define	DCRN_EXISR_BASE		0x040
#define	DCRN_IOCR_BASE		0x0A0


/* ------------------------------------------------------------------------- */
#endif



#ifdef DCRN_BE_BASE
#define	DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
#define	DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register*/
#endif
/* DCRN_BESR */
#define BESR_DSES	0x80000000	/* Data-Side Error Status */
#define BESR_DMES	0x40000000	/* DMA Error Status */
#define BESR_RWS	0x20000000	/* Read/Write Status */
#define BESR_ETMASK	0x1C000000	/* Error Type */
#define ET_PROT	0
#define ET_PARITY	1
#define ET_NCFG	2
#define ET_BUSERR	4
#define ET_BUSTO	6

#ifdef DCRN_CHCR_BASE
#define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
#define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
#endif
#define CHR1_CETE	0x00800000		 /* CPU external timer enable */
#define CHR1_PCIPW	0x00008000 /* PCI Int enable/Peripheral Write enable */

#ifdef DCRN_CHPSR_BASE
#define DCRN_CHPSR	(DCRN_CHPSR_BASE + 0x0)	/* Chip Pin Strapping */
#endif

#ifdef DCRN_CIC_BASE
#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
#endif

#ifdef DCRN_CPMFR_BASE
#define DCRN_CPMFR	(DCRN_CPMFR_BASE + 0x0)	/* CPM Force */
#endif

#ifndef CPM_AUD
#define CPM_AUD		0x00000000
#endif
#ifndef CPM_BRG
#define CPM_BRG		0x00000000
#endif
#ifndef CPM_CBS
#define CPM_CBS		0x00000000
#endif
#ifndef CPM_CPU
#define CPM_CPU		0x00000000
#endif
#ifndef CPM_DCP
#define CPM_DCP		0x00000000
#endif
#ifndef CPM_DCRX
#define CPM_DCRX	0x00000000
#endif
#ifndef CPM_DENC
#define CPM_DENC	0x00000000
#endif
#ifndef CPM_DMA
#define CPM_DMA		0x00000000
#endif
#ifndef CPM_DSCR
#define CPM_DSCR	0x00000000
#endif
#ifndef CPM_EBC
#define CPM_EBC		0x00000000
#endif
#ifndef CPM_EBIU
#define CPM_EBIU	0x00000000
#endif
#ifndef CPM_EMAC_MM
#define CPM_EMAC_MM	0x00000000
#endif
#ifndef CPM_EMAC_RM
#define CPM_EMAC_RM	0x00000000
#endif
#ifndef CPM_EMAC_TM
#define CPM_EMAC_TM	0x00000000
#endif
#ifndef CPM_GPIO0
#define CPM_GPIO0	0x00000000
#endif
#ifndef CPM_GPT
#define CPM_GPT		0x00000000
#endif
#ifndef CPM_I1284
#define CPM_I1284	0x00000000
#endif
#ifndef CPM_IIC0
#define CPM_IIC0	0x00000000
#endif
#ifndef CPM_IIC1
#define CPM_IIC1	0x00000000
#endif
#ifndef CPM_MSI
#define CPM_MSI		0x00000000
#endif
#ifndef CPM_PCI
#define CPM_PCI		0x00000000
#endif
#ifndef CPM_PLB
#define CPM_PLB		0x00000000
#endif
#ifndef CPM_SC0
#define CPM_SC0		0x00000000
#endif
#ifndef CPM_SC1
#define CPM_SC1		0x00000000
#endif
#ifndef CPM_SDRAM0
#define CPM_SDRAM0	0x00000000
#endif
#ifndef CPM_SDRAM1
#define CPM_SDRAM1	0x00000000
#endif
#ifndef CPM_TMRCLK
#define CPM_TMRCLK	0x00000000
#endif
#ifndef CPM_UART0
#define CPM_UART0	0x00000000
#endif
#ifndef CPM_UART1
#define CPM_UART1	0x00000000
#endif
#ifndef CPM_UART2
#define CPM_UART2	0x00000000
#endif
#ifndef CPM_UIC
#define CPM_UIC		0x00000000
#endif
#ifndef CPM_VID2
#define CPM_VID2	0x00000000
#endif
#ifndef CPM_XPT27
#define CPM_XPT27	0x00000000
#endif
#ifndef CPM_XPT54
#define CPM_XPT54	0x00000000
#endif

#ifdef DCRN_CPMSR_BASE
#define DCRN_CPMSR	(DCRN_CPMSR_BASE + 0x0)	/* CPM Status */
#define DCRN_CPMER	(DCRN_CPMSR_BASE + 0x1)	/* CPM Enable */
#endif

#ifdef DCRN_DCP0_BASE
#define DCRN_DCP0_CFGADDR	(DCRN_DCP0_BASE + 0x0)	/* Decompression Controller Address */
#define DCRN_DCP0_CFGDATA	(DCRN_DCP0_BASE + 0x1)	/* Decompression Controller Data */
#endif

#ifdef DCRN_DCRX_BASE
#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
#endif

#ifdef DCRN_DMA0_BASE
#define	DCRN_DMACR0	(DCRN_DMA0_BASE + 0x0)	/* DMA Channel Control Register 0 */
#define	DCRN_DMACT0	(DCRN_DMA0_BASE + 0x1)	/* DMA Count Register 0 */
#define	DCRN_DMADA0	(DCRN_DMA0_BASE + 0x2)	/* DMA Destination Address Register 0 */
#define	DCRN_DMASA0	(DCRN_DMA0_BASE + 0x3)	/* DMA Source Address Register 0 */
#ifdef DCRNCAP_DMA_CC
#define	DCRN_DMACC0	(DCRN_DMA0_BASE + 0x4)	/* DMA Chained Count Register 0 */
#endif

#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG0	(DCRN_DMA0_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 0 */
#endif
#endif

#ifdef DCRN_DMA1_BASE
#define	DCRN_DMACR1	(DCRN_DMA1_BASE + 0x0)	/* DMA Channel Control Register 1 */
#define	DCRN_DMACT1	(DCRN_DMA1_BASE + 0x1)	/* DMA Count Register 1 */
#define	DCRN_DMADA1	(DCRN_DMA1_BASE + 0x2)	/* DMA Destination Address Register 1 */
#define	DCRN_DMASA1	(DCRN_DMA1_BASE + 0x3)	/* DMA Source Address Register 1 */

#ifdef DCRNCAP_DMA_CC
#define	DCRN_DMACC1	(DCRN_DMA1_BASE + 0x4)	/* DMA Chained Count Register 1 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG1	(DCRN_DMA1_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 1 */
#endif
#endif

#ifdef DCRN_DMA2_BASE
#define	DCRN_DMACR2	(DCRN_DMA2_BASE + 0x0)	/* DMA Channel Control Register 2 */
#define	DCRN_DMACT2	(DCRN_DMA2_BASE + 0x1)	/* DMA Count Register 2 */
#define	DCRN_DMADA2	(DCRN_DMA2_BASE + 0x2)	/* DMA Destination Address Register 2 */
#define	DCRN_DMASA2	(DCRN_DMA2_BASE + 0x3)	/* DMA Source Address Register 2 */
#ifdef DCRNCAP_DMA_CC
#define	DCRN_DMACC2	(DCRN_DMA2_BASE + 0x4)	/* DMA Chained Count Register 2 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG2	(DCRN_DMA2_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 2 */