dma.h

Linux Kernel 2.6.9 for OMAP1710

/* 
 * linux/include/asm-arm/arch-omap2/dma.h
 * 
 * Defines for OMAP2 DMA
 *
 * Copyright (C) 2003 Nokia Corporation
 * Author: Juha Yrjölä <[e-mail]>
 *
 * Copyright (C) 2004 Texas Instruments, Inc. 
 * 
 * This package is free software; you can redistribute it and/or modify 
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation. 
 * 
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 
 */

#ifndef __ASM_ARM_ARCH_OMAP2_DMA_H
#define __ASM_ARM_ARCH_OMAP2_DMA_H

#define MAX_DMA_ADDRESS                 0xffffffff

#define OMAP_DMA_TOUT_IRQ               (1 << 0)
#define OMAP_DMA_DROP_IRQ               (1 << 1)
#define OMAP_DMA_HALF_IRQ               (1 << 2)
#define OMAP_DMA_FRAME_IRQ              (1 << 3)
#define OMAP_DMA_LAST_IRQ               (1 << 4)
#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
#define OMAP_DMA_SYNC_IRQ               (1 << 6)

#define OMAP_DMA_DATA_TYPE_S8           0x00
#define OMAP_DMA_DATA_TYPE_S16          0x01
#define OMAP_DMA_DATA_TYPE_S32          0x02

#define OMAP_DMA_SYNC_ELEMENT           0x00
#define OMAP_DMA_SYNC_FRAME             0x01
#define OMAP_DMA_SYNC_BLOCK             0x02

#define OMAP_DMA_PORT_EMIFF             0x00
#define OMAP_DMA_PORT_EMIFS             0x01
#define OMAP_DMA_PORT_OCP_T1            0x02
#define OMAP_DMA_PORT_TIPB              0x03
#define OMAP_DMA_PORT_OCP_T2            0x04
#define OMAP_DMA_PORT_MPUI              0x05

#define OMAP_DMA_AMODE_CONSTANT         0x00
#define OMAP_DMA_AMODE_POST_INC         0x01
#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03

#define OMAP_DMA_USB_W2FC_TX0		54
#define OMAP_DMA_USB_W2FC_RX0		55
#define OMAP_DMA_USB_W2FC_TX1		56
#define OMAP_DMA_USB_W2FC_RX1		57
#define OMAP_DMA_USB_W2FC_TX2		58
#define OMAP_DMA_USB_W2FC_RX2		59

#define OMAP_DMA4_BASE_VIRT             IO_ADDRESS(0x48056000)
#define OMAP_DMA4_BASE_PHYS             0x48056000
#define OMAP_DMA4_BASE                  OMAP_DMA4_BASE_VIRT

#define OMAP_DMA4_GCR_REG               (OMAP_DMA_BASE + 0x78)

#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)

#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)

#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)

#define OMAP_DMA4_CAPS_0_REG            (OMAP_DMA4_BASE + 0x64)
#define OMAP_DMA4_CAPS_2_REG            (OMAP_DMA4_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3_REG            (OMAP_DMA4_BASE + 0x70)
#define OMAP_DMA4_CAPS_4_REG            (OMAP_DMA4_BASE + 0x74)

/* Every LCh has its own set of the registers below */

#define OMAP_DMA4_CCR_REG(n)            (OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA4_CLNK_CTRL_REG(n)      (OMAP_DMA4_BASE + 0x60 * (n) + 0x84)

#define OMAP_DMA4_CICR_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
#define OMAP_DMA4_CSR_REG(n)            (OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)

#define OMAP_DMA4_CSDP_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
#define OMAP_DMA4_CEN_REG(n)            (OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
#define OMAP_DMA4_CFN_REG(n)            (OMAP_DMA4_BASE + 0x60 * (n) + 0x98)

#define OMAP_DMA4_CSSA_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
#define OMAP_DMA4_CDSA_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)

#define OMAP_DMA4_CSEI_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
#define OMAP_DMA4_CSFI_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
#define OMAP_DMA4_CDEI_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
#define OMAP_DMA4_CDFI_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)

#define OMAP_DMA4_CSAC_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
#define OMAP_DMA4_CDAC_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
#define OMAP_DMA4_CCEN_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
#define OMAP_DMA4_CCFN_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)

#define OMAP_DMA_COLOR_REG(n)           (OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)

#define OMAP24XX_LOGICAL_DMA_CH_COUNT   32

#define OMAP_DMA_CHAINING_SUPPORT

/*
 * All possible OMAP2420 devices a DMA channel can be attached to.
 */
typedef enum {
	eDMANotSync,		// 0
	eMCSI1Tx,
	eMCSI1Rx,
	eI2CRx,
	eI2CTx,
	eExt0,			// 5
	eExt1,
	eMicroWireTx,
	eAudioTx,
	eAudioRx,
	eOpticalTx,		// 10
	eOpticalRx,
	eBluetoothTx,
	eBluetoothRx,
	eModemTx,
	eModemRx,		// 15
	eModemDataTx,
	eModemDataRx,
	eUART3Tx,
	eUART3Rx,
	eCameraRx,		// 20
	eMMCTx,
	eMMCRx,
	eNANDEoB,
	eIRQLCDLINE,
	eMemoryStick,		// 25
	eUSBRx0,
	eUSBRx1,
	eUSBRx2,
	eUSBTx0,
	eUSBTx1,		// 30
	eUSBTx2,
	eDESin,
	eSPITx,
	eSPIRx,
	eSHAMD5,		// 35
	eCCPAttn,
	eCCPFIFOne,
	eCMTAPETx0,
	eCMTAPERx0,
	eCMTAPETx1,		// 40
	eCMTAPERx1,
	eCMTAPETx2,
	eCMTAPERx2,
	eCMTAPETx3,
	eCMTAPERx3,		// 45
	eCMTAPETx4,
	eCMTAPERx4,
	eCMTAPETx5,
	eCMTAPERx5,
	eCMTAPETx6,		// 50
	eCMTAPERx6,
	eCMTAPETx7,
	eCMTAPERx7,
	eMMC2Tx,
	eMMC2Rx,		// 55
	eDESout,
} dma_device_t;

typedef enum {
	eDmaIn,
	eDmaOut
} dma_direction_t;

/*
 * DMA control register structure, without LCD registers
 */
typedef struct {
	volatile u16 csdp;	// channel s/d parameters -- working set (current transfer)
	volatile u16 ccr;	// channel control -- working set
	volatile u16 cicr;	// channel interrupt control -- working set
	volatile u16 csr;	// channel status -- working set
	volatile u16 cssa_l;	// source lower bits -- programming set (next transfer)
	volatile u16 cssa_u;	// source upper bits -- programming set
	volatile u16 cdsa_l;	// destn lower bits -- programming set
	volatile u16 cdsa_u;	// destn upper bits -- programming set
	volatile u16 cen;	// channel element number -- programming set
	volatile u16 cfn;	// channel frame number -- programming set
	volatile u16 csfi;	// channel source frame index -- programming set
	volatile u16 csei;	// channel source element index -- programming set
	volatile u16 csac;	// channel source address counter
	volatile u16 cdac;	// channel dest. address counter
	volatile u16 cdei;	// channel dest. element index -- programming set
	volatile u16 cdfi;	// channel dest. frame index -- programming set
	volatile u16 color_l;	// graphics&LCD channels color - lower bits
	volatile u16 color_u;	// graphics&LCD channels color - upper bits
	volatile u16 ccr2;	// channel control 2
	volatile u16 reserved;	// reserved
	volatile u16 clink_ctrl;	// link control
	volatile u16 lch_ctrl;	// channel type control
	volatile u16 null[10];	// for alignment
} dma_regs_t;

typedef struct lch_chain_t {
	int num_channels;
	int queue_head;		/* head of the queue , this is the channel which is currently running */
	int queue_tail;		/* tail of the queue , this is the last channel which was queued */
	int started;
	int queued;
} lch_chain;
/* sync_mode
sync_mode	FS 	BS
	0x0	0 	0 	- an element is transferred once a dma
	0x1	0 	1	- an entire block is transferred once a dma
	0x2	1 	0	- an entire frame is transferred once a dma
	0x3	1 	1	- a packet is transferred once a dma
*/

typedef struct dma_channel_params_t {
	int data_type;		/* data type 8,16,32 */
	int elem_count;		/* number of elements in a frame */
	int frame_count;	/* number of frames in a element */

	int src_amode;		/* constant , post increment, indexed , double indexed */
	int src_start;		/* source address : physical */
	int src_ei;		/* source element index */
	int src_fi;		/* source frame index */

	int dst_amode;		/* constant , post increment, indexed , double indexed */
	int dst_start;		/* source address : physical */
	int dst_ei;		/* source element index */
	int dst_fi;		/* source frame index */

	int trigger;		/* trigger attached if the channel is synchronized */
	int sync_mode;		/* sycn on element, frame , block or packet */
	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */

	int ie;			/* interrupt enabled */
} dma_channel_params;

/* simple dma routines */
extern int omap_request_dma(int dev_id, const char *dev_name,
			void (* callback)(int lch, u16 ch_status, void *data),
			void *data, int *dma_ch_out);

extern void omap_free_dma(int ch);
extern int omap_start_dma(int lch);
extern void omap_stop_dma(int lch);

extern void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
			int frame_count, int sync_mode, int dma_trigger,
			int src_or_dst_synch);

extern void omap_set_dma_src_params(int lch, int src_amode,
			int src_start,int src_ei, int src_fi );

extern void omap_set_dma_dest_params(int lch, int dest_amode,
			int dest_start, int dst_ei, int dst_fi);

extern void omap_set_dma_params(int lch, dma_channel_params params);

extern void omap_disable_dma_irq(int ch);

/*internal */
void omap_enable_dma_irq(int ch);
/* chain functions exported */
extern int omap_request_dma_chain(int dev_id, const char *dev_name,
			int num_transfers,
			void (* callback)(int lch, u16 ch_status, void *data),
			void *data, int *dma_ch_out, lch_chain** chain);

extern void omap_free_dma_chain(lch_chain *chain);
extern void omap_stop_dma_chain(lch_chain *chain);
extern int omap_start_dma_chain(lch_chain *chain);
extern int omap_set_dma_params_chain(lch_chain *chain,
			dma_channel_params params);

/* chain functions not exported - internal*/
void disable_chain(int lch);
void enable_chain(int lch1, int lch2);	/* next dma transfer queued */
void remove_chain(int lch);
void setup_chain(int lch1, int lch2);

int omap_get_dma_pos_src(int lch);
int omap_get_dma_pos_dst(int lch);
void omap_clear_dma_chain(lch_chain * chain);

#endif				/* __ASM_ARM_ARCH_OMAP2_DMA_H */