hardware.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 251 行
H
251 行
/* * linux/include/asm-arm/arch-omap2/hardware.h * * This file contains the hardware definitions of the TI H4 SDP. * * Copyright (C) 2004 Texas Instruments, Inc. * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */#ifndef __ASM_ARM_ARCH_OMAP2_HARDWARE_H#define __ASM_ARM_ARCH_OMAP2_HARDWARE_H#include <asm/arch/cpu.h>#include <asm/sizes.h>/* * L3 Peripherals */#define OMAP24XX_L3_IO_BASE 0x68000000/* GPMC */#define OMAP2420_GPMC_BASE (OMAP24XX_L3_IO_BASE+0xA000)#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)/* SMS */#define OMAP2420_SMS_BASE (OMAP24XX_L3_IO_BASE+0x8000)#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)/* SDRC */#define OMAP2420_SDRC_BASE (OMAP24XX_L3_IO_BASE+0x9000)#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)#define OMAP2420_SDRC_CS0 0x80000000#define OMAP2420_SDRC_CS1 0xA0000000#define CMD_NOP 0x0#define CMD_PRECHARGE 0x1#define CMD_AUTOREFRESH 0x2#define CMD_ENTR_PWRDOWN 0x3#define CMD_EXIT_PWRDOWN 0x4#define CMD_ENTR_SRFRSH 0x5#define CMD_CKE_HIGH 0x6#define CMD_CKE_LOW 0x7#define SOFTRESET BIT1#define SMART_IDLE (0x2 << 3)#define REF_ON_IDLE (0x1 << 6)/* * L4 Periferals */#define OMAP24XX_L4_IO_BASE 0x48000000/* CONTROL */#define OMAP2420_CTRL_BASE (OMAP24XX_L4_IO_BASE+0x0)#define CONTROL_STATUS (OMAP2420_CTRL_BASE+0x2F8)#define OMAP24XX_SYSTEM_CONTROL_BASE (OMAP24XX_L4_IO_BASE+0x0)#define OMAP24XX_VA_SYSTEM_CONTROL_BASE IO_ADDRESS(OMAP24XX_SYSTEM_CONTROL_BASE)/* TAP information */#define OMAP2420_TAP_BASE (OMAP24XX_L4_IO_BASE+0x14000)#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)/* UART */#define OMAP24XX_UART1_BASE (OMAP24XX_L4_IO_BASE+0x6a000)#define OMAP24XX_UART2_BASE (OMAP24XX_L4_IO_BASE+0x6c000)#define OMAP24XX_UART3_BASE (OMAP24XX_L4_IO_BASE+0x6e000)/* USB */#define OMAP24XX_OHCI_BASE (OMAP24XX_L4_IO_BASE+0x5e000)#define OMAP24XX_UDC_BASE (OMAP24XX_L4_IO_BASE+0x5e200)#define OMAP24XX_OTG_BASE (OMAP24XX_L4_IO_BASE+0x5e300)/* General Purpose Timers */#define OMAP2420_GPT1 (OMAP24XX_L4_IO_BASE+0x28000)#define OMAP2420_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)#define OMAP2420_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)#define OMAP2420_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)#define OMAP2420_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)#define OMAP2420_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)#define OMAP2420_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)#define OMAP2420_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)#define OMAP2420_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)#define OMAP2420_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)#define OMAP2420_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)#define OMAP2420_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)#define OMAP24XX_GPTIMER_OFF 0x2000#define OMAP24XX_TIMER1_BASE 0x48028000#define OMAP24XX_TIMER2_BASE (OMAP24XX_TIMER1_BASE+OMAP24XX_GPTIMER_OFF)#define OMAP24XX_TIMER3_BASE 0x48078000#define OMAP24XX_TIMER4_BASE (OMAP24XX_TIMER3_BASE+OMAP24XX_GPTIMER_OFF)/* GPMC regs offsets (32 bit regs) */#define OFFSET_CONFIG1_0 0x60#define OFFSET_NAND_COMMAND_0 0x7C#define OFFSET_NAND_ADDRESS_0 0x80#define OFFSET_NAND_DATA_0 0x84#define OFFSET_CONFIG 0x50#define OFFSET_STATUS 0x54/* timer regs offsets (32 bit regs) */#define TIDR 0x00 /* r */#define TIOCP_CFG 0x10 /* rw */#define TISTAT 0x14 /* r */#define TISR 0x18 /* rw */#define TIER 0x1C /* rw */#define TWER 0x20 /* rw */#define TCLR 0x24 /* rw */#define TCRR 0x28 /* rw */#define TLDR 0x2C /* rw */#define TTGR 0x30 /* rw */#define TWPS 0x34 /* r */#define TMAR 0x38 /* rw */#define TCAR1 0x3c /* r */#define TSICR 0x40 /* rw */#define TCAR2 0x44 /* r *//* Timer 32K omap*/#define OMAP_TIMER32K_BASE (OMAP24XX_L4_IO_BASE+0x4000)/* WatchDog Timers (1 secure, 3 GP) */#define WD1_BASE (OMAP24XX_L4_IO_BASE+0x20000)#define WD2_BASE (OMAP24XX_L4_IO_BASE+0x22000)#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000)#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000)#define WWPS 0x34 /* r */#define WSPR 0x48 /* rw */#define WD_UNLOCK1 0xAAAA#define WD_UNLOCK2 0x5555/* Watchdog Timer 2*/#define OMAP24XX_WDTIMER2_BASE (OMAP24XX_L4_IO_BASE+0x22000)#define OMAP24XX_VA_WDTIMER2_BASE IO_ADDRESS(OMAP24XX_WDTIMER2_BASE)/* PRCM -- need to rework when power managment comes */#define OMAP24XX_PRCM_BASE (OMAP24XX_L4_IO_BASE+0x8000)#define OMAP24XX_VA_PRCM_BASE IO_ADDRESS(OMAP24XX_PRCM_BASE)#define OMAP2420_CM_BASE (OMAP24XX_L4_IO_BASE+0x8000)#define PRCM_BASE_ADDRESS OMAP24XX_VA_PRCM_BASE#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)#define CM_CLKEN_PLL (0x500)#define CM_IDLEST_GEN (0x520)#define CM_AUTOIDLE_PLL (0x530)#define CM_CLKSEL1_PLL (0x540)#define CM_CLKSEL2_PLL (0x544)/* PRCM CORE Domain registers offsets */#define CM_FCLKEN1_CORE (0x200)#define CM_FCLKEN2_CORE (0x204)#define CM_ICLKEN1_CORE (0x210)#define CM_ICLKEN2_CORE (0x214)#define CM_ICLKEN4_CORE (0x21C)#define CM_IDLEST1_CORE (0x220)#define CM_IDLEST2_CORE (0x224)#define CM_IDLEST4_CORE (0x22C)#define CM_AUTOIDLE1_CORE (0x230)#define CM_AUTOIDLE2_CORE (0x234)#define CM_AUTOIDLE3_CORE (0x238)#define CM_AUTOIDLE4_CORE (0x23C)#define CM_CLKSEL1_CORE (0x240)#define CM_CLKSEL2_CORE (0x244)#define CM_CLKSTCTRL_CORE (0x248)#define PM_WKEN1_CORE (0x2A0)#define PM_WKEN2_CORE (0x2A4)#define PM_WKST1_CORE (0x2B0)#define PM_WKST2_CORE (0x2B4)#define PM_WKDEP_CORE (0x2C8)#define PM_PWSTCTRL_CORE (0x2E0)#define PM_PWSTST_CORE (0x2E4)#define PRCM_RM_RSTST_WKUP (0x458)#define PRCM_RM_RSTST_WKUP (0x458)#define PRCM_CM_FCLKEN_WKUP (0x400)#define PRCM_CM_ICLKEN_WKUP (0x410)/* interrupt controller */#define OMAP24XX_IC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)#define OMAP24XX_IH_BASE VA_IC_BASE#define OMAP24XX_IH_0_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + IH_0_BASE_OFFSET#define OMAP24XX_IH_1_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + IH_1_BASE_OFFSET#define OMAP24XX_IH_2_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + IH_2_BASE_OFFSET#define OMAP24XX_ILR_BASE IO_ADDRESS(OMAP24XX_IC_BASE) + ILR_BASE_OFFSET#define IH_0_BASE_OFFSET 0x80#define IH_1_BASE_OFFSET 0xa0#define IH_2_BASE_OFFSET 0xc0#define ILR_BASE_OFFSET 0x100#define IRQ_REVISION 0x0000#define IRQ_SYSCONFIG 0x0010#define IRQ_SYSSTATUS 0x0014#define IRQ_SIR_IRQ 0x0040#define IRQ_SIR_FIQ 0x0044#define IRQ_CONTROL_REG 0x0048#define IRQ_PROTECTION 0x004C#define IRQ_IDLE 0x0050/* group 2,3,4 */#define IRQ_ITR 0x0000#define IRQ_MIR 0x0004#define IRQ_MIR_CLEAR 0x0008#define IRQ_MIR_SET 0x000C#define IRQ_ISR_SET 0x0010#define IRQ_ISR_CLEAR 0x0014#define IRQ_PENDING_IRQ 0x0018#define IRQ_PENDING_FIQ 0x001C/* OMAP24XX GPIO block base */#define OMAP24XX_GPIO_BASE (OMAP24XX_L4_IO_BASE+0x18000)/* EAC */#define EAC_BASE_ADDR_PHYS (OMAP24XX_L4_IO_BASE+0x90000)#endif /* __ASM_ARM_ARCH_OMAP2_HARDWARE_H */⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?