mux-omap16xx.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 350 行 · 第 1/2 页
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350 行
/* * linux/include/asm-arm/arch-omap/mux-omap16xx.h * * Table of the Omap register configurations for the FUNC_MUX and * PULL_DWN combinations. * * Copyright (C) 2003 Nokia Corporation * * Written by Tony Lindgren <tony.lindgren@nokia.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * NOTE: Please use the following naming style for new pin entries. * For example, W8_1610_MMC2_DAT0, where: * - W8 = ball * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 * - MMC2_DAT0 = function * * Change log: * Added entry for the I2C interface. (02Feb 2004) * Copyright (C) 2004 Texas Instruments * * Added entry for the keypad and uwire CS1. (09Mar 2004) * Copyright (C) 2004 Texas Instruments * * Renamed as mux-omap16xx.h containing the omap1x specific defines (28Aug 2004) * Copyright (C) 2004 Texas Instruments * */#ifndef __ASM_ARCH_MUX_OMAP_H#define __ASM_ARCH_MUX_OMAP_H#define PU_PD_SEL_NA 0 /* No pu_pd reg available */#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */#ifdef CONFIG_OMAP_MUX_DEBUG#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ .mux_reg = FUNC_MUX_CTRL_##reg, \ .mask_offset = mode_offset, \ .mask = mode,#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ .pull_reg = PULL_DWN_CTRL_##reg, \ .pull_bit = bit, \ .pull_val = status,#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status,#else#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ .mask_offset = mode_offset, \ .mask = mode,#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ .pull_bit = bit, \ .pull_val = status,#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status,#endif /* CONFIG_OMAP_MUX_DEBUG */#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ pull_reg, pull_bit, pull_status, \ pu_pd_reg, pu_pd_status, debug_status) \{ \ .name = desc, \ .debug = debug_status, \ MUX_REG(mux_reg, mode_offset, mode) \ PULL_REG(pull_reg, pull_bit, pull_status) \ PU_PD_REG(pu_pd_reg, pu_pd_status) \},#define PULL_DISABLED 0#define PULL_ENABLED 1#define PULL_DOWN 0#define PULL_UP 1typedef struct { char *name; unsigned char busy; unsigned char debug; const char *mux_reg_name; const unsigned int mux_reg; const unsigned char mask_offset; const unsigned char mask; const char *pull_name; const unsigned int pull_reg; const unsigned char pull_val; const unsigned char pull_bit; const char *pu_pd_name; const unsigned int pu_pd_reg; const unsigned char pu_pd_val;} reg_cfg_set;#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)/* * Table of various FUNC_MUX and PULL_DWN combinations for each device. * See also reg_cfg_t above for the lookup table. */static reg_cfg_set __initdata_or_modulereg_cfg_table[] = {/* * description mux mode mux pull pull pull pu_pd pu dbg * reg offset mode reg bit ena reg */MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)/* UART2 (COM_UART_GATING), conflicts with USB2 */MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)/* UART3 (GIGA_UART_GATING) */MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)/* PWT & PWL, conflicts with UART3 */MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)/* USB internal master generic */MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)MUX_CFG("W4_USB_PUEN", D, 3, 0, 3, 5, 1, NA, 0, 1)MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)/* USB1 master */MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)/* USB2 master */MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
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