bitops.h

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#ifndef _S390_BITOPS_H
#define _S390_BITOPS_H

/*
 *  include/asm-s390/bitops.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Martin Schwidefsky ([e-mail])
 *
 *  Derived from "include/asm-i386/bitops.h"
 *    Copyright (C) 1992, Linus Torvalds
 *
 */
#include <linux/config.h>
#include <linux/compiler.h>

/*
 * 32 bit bitops format:
 * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr;
 * bit 32 is the LSB of *(addr+4). That combined with the
 * big endian byte order on S390 give the following bit
 * order in memory:
 *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \
 *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
 * after that follows the next long with bit numbers
 *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
 *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
 * The reason for this bit ordering is the fact that
 * in the architecture independent code bits operations
 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
 * with operation of the form "set_bit(bitnr, flags)".
 *
 * 64 bit bitops format:
 * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr;
 * bit 64 is the LSB of *(addr+8). That combined with the
 * big endian byte order on S390 give the following bit
 * order in memory:
 *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
 *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
 *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10
 *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
 * after that follows the next long with bit numbers
 *    7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70
 *    6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60
 *    5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50
 *    4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40
 * The reason for this bit ordering is the fact that
 * in the architecture independent code bits operations
 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
 * with operation of the form "set_bit(bitnr, flags)".
 */

/* set ALIGN_CS to 1 if the SMP safe bit operations should
 * align the address to 4 byte boundary. It seems to work
 * without the alignment. 
 */
#ifdef __KERNEL__
#define ALIGN_CS 0
#else
#define ALIGN_CS 1
#ifndef CONFIG_SMP
#error "bitops won't work without CONFIG_SMP"
#endif
#endif

/* bitmap tables from arch/S390/kernel/bitmap.S */
extern const char _oi_bitmap[];
extern const char _ni_bitmap[];
extern const char _zb_findmap[];
extern const char _sb_findmap[];

#ifndef __s390x__

#define __BITOPS_ALIGN		3
#define __BITOPS_WORDSIZE	32
#define __BITOPS_OR		"or"
#define __BITOPS_AND		"nr"
#define __BITOPS_XOR		"xr"

#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)		\
	__asm__ __volatile__("   l   %0,0(%4)\n"			\
			     "0: lr  %1,%0\n"				\
			     __op_string "  %1,%3\n"			\
			     "   cs  %0,%1,0(%4)\n"			\
			     "   jl  0b"				\
			     : "=&d" (__old), "=&d" (__new),	       	\
			       "=m" (*(unsigned long *) __addr)		\
			     : "d" (__val), "a" (__addr),		\
			       "m" (*(unsigned long *) __addr) : "cc" );

#else /* __s390x__ */

#define __BITOPS_ALIGN		7
#define __BITOPS_WORDSIZE	64
#define __BITOPS_OR		"ogr"
#define __BITOPS_AND		"ngr"
#define __BITOPS_XOR		"xgr"

#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)		\
	__asm__ __volatile__("   lg  %0,0(%4)\n"			\
			     "0: lgr %1,%0\n"				\
			     __op_string "  %1,%3\n"			\
			     "   csg %0,%1,0(%4)\n"			\
			     "   jl  0b"				\
			     : "=&d" (__old), "=&d" (__new),	       	\
			       "=m" (*(unsigned long *) __addr)		\
			     : "d" (__val), "a" (__addr),		\
			       "m" (*(unsigned long *) __addr) : "cc" );

#endif /* __s390x__ */

#define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
#define __BITOPS_BARRIER() __asm__ __volatile__ ( "" : : : "memory" )

#ifdef CONFIG_SMP
/*
 * SMP safe set_bit routine based on compare and swap (CS)
 */
static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;    /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	       /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make OR mask */
	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
}

/*
 * SMP safe clear_bit routine based on compare and swap (CS)
 */
static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;    /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	       /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make AND mask */
	mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
}

/*
 * SMP safe change_bit routine based on compare and swap (CS)
 */
static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;    /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	       /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make XOR mask */
	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
}

/*
 * SMP safe test_and_set_bit routine based on compare and swap (CS)
 */
static inline int
test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;    /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	       /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make OR/test mask */
	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
	__BITOPS_BARRIER();
	return (old & mask) != 0;
}

/*
 * SMP safe test_and_clear_bit routine based on compare and swap (CS)
 */
static inline int
test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;    /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	       /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make AND/test mask */
	mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
	__BITOPS_BARRIER();
	return (old ^ new) != 0;
}

/*
 * SMP safe test_and_change_bit routine based on compare and swap (CS) 
 */
static inline int
test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
{
        unsigned long addr, old, new, mask;

	addr = (unsigned long) ptr;
#if ALIGN_CS == 1
	nr += (addr & __BITOPS_ALIGN) << 3;  /* add alignment to bit number */
	addr ^= addr & __BITOPS_ALIGN;	     /* align address to 8 */
#endif
	/* calculate address for CS */
	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
	/* make XOR/test mask */
	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
	/* Do the atomic update. */
	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
	__BITOPS_BARRIER();
	return (old & mask) != 0;
}
#endif /* CONFIG_SMP */

/*
 * fast, non-SMP set_bit routine
 */
static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        asm volatile("oc 0(1,%1),0(%2)"
		     : "=m" (*(char *) addr)
		     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
		       "m" (*(char *) addr) : "cc" );
}

static inline void 
__constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
	switch (nr&7) {
	case 0:
		asm volatile ("oi 0(%1),0x01" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 1:
		asm volatile ("oi 0(%1),0x02" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 2:
		asm volatile ("oi 0(%1),0x04" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 3:
		asm volatile ("oi 0(%1),0x08" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 4:
		asm volatile ("oi 0(%1),0x10" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 5:
		asm volatile ("oi 0(%1),0x20" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 6:
		asm volatile ("oi 0(%1),0x40" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 7:
		asm volatile ("oi 0(%1),0x80" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	}
}

#define set_bit_simple(nr,addr) \
(__builtin_constant_p((nr)) ? \
 __constant_set_bit((nr),(addr)) : \
 __set_bit((nr),(addr)) )

/*
 * fast, non-SMP clear_bit routine
 */
static inline void 
__clear_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        asm volatile("nc 0(1,%1),0(%2)"
		     : "=m" (*(char *) addr)
		     : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
		       "m" (*(char *) addr) : "cc" );
}

static inline void 
__constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
	switch (nr&7) {
	case 0:
		asm volatile ("ni 0(%1),0xFE" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 1:
		asm volatile ("ni 0(%1),0xFD": "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 2:
		asm volatile ("ni 0(%1),0xFB" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 3:
		asm volatile ("ni 0(%1),0xF7" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 4:
		asm volatile ("ni 0(%1),0xEF" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 5:
		asm volatile ("ni 0(%1),0xDF" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 6:
		asm volatile ("ni 0(%1),0xBF" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 7:
		asm volatile ("ni 0(%1),0x7F" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	}
}

#define clear_bit_simple(nr,addr) \
(__builtin_constant_p((nr)) ? \
 __constant_clear_bit((nr),(addr)) : \
 __clear_bit((nr),(addr)) )

/* 
 * fast, non-SMP change_bit routine 
 */
static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
        asm volatile("xc 0(1,%1),0(%2)"
		     :  "=m" (*(char *) addr)
		     : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
		       "m" (*(char *) addr) : "cc" );
}

static inline void 
__constant_change_bit(const unsigned long nr, volatile unsigned long *ptr) 
{
	unsigned long addr;

	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
	switch (nr&7) {
	case 0:
		asm volatile ("xi 0(%1),0x01" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );
		break;
	case 1:
		asm volatile ("xi 0(%1),0x02" : "=m" (*(char *) addr)
			      : "a" (addr), "m" (*(char *) addr) : "cc" );