mc68328.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件代码 · 共 1,267 行 · 第 1/3 页
1,267 行
 * 0xFFFFF4xx -- Parallel Ports * **********//* * Port A */#define PADIR_ADDR	0xfffff400		/* Port A direction reg */#define PADATA_ADDR	0xfffff401		/* Port A data register */#define PASEL_ADDR	0xfffff403		/* Port A Select register */#define PADIR		BYTE_REF(PADIR_ADDR)#define PADATA		BYTE_REF(PADATA_ADDR)#define PASEL		BYTE_REF(PASEL_ADDR)#define PA(x)           (1 << (x))#define PA_A(x)		PA((x) - 16)	/* This is specific to PA only! */#define PA_A16		PA(0)		/* Use A16 as PA(0) */#define PA_A17		PA(1)		/* Use A17 as PA(1) */#define PA_A18		PA(2)		/* Use A18 as PA(2) */#define PA_A19		PA(3)		/* Use A19 as PA(3) */#define PA_A20		PA(4)		/* Use A20 as PA(4) */#define PA_A21		PA(5)		/* Use A21 as PA(5) */#define PA_A22		PA(6)		/* Use A22 as PA(6) */#define PA_A23		PA(7)		/* Use A23 as PA(7) *//*  * Port B */#define PBDIR_ADDR	0xfffff408		/* Port B direction reg */#define PBDATA_ADDR	0xfffff409		/* Port B data register */#define PBSEL_ADDR	0xfffff40b		/* Port B Select Register */#define PBDIR		BYTE_REF(PBDIR_ADDR)#define PBDATA		BYTE_REF(PBDATA_ADDR)#define PBSEL		BYTE_REF(PBSEL_ADDR)#define PB(x)           (1 << (x))#define PB_D(x)		PB(x)		/* This is specific to port B only */#define PB_D0		PB(0)		/* Use D0 as PB(0) */#define PB_D1		PB(1)		/* Use D1 as PB(1) */#define PB_D2		PB(2)		/* Use D2 as PB(2) */#define PB_D3		PB(3)		/* Use D3 as PB(3) */#define PB_D4		PB(4)		/* Use D4 as PB(4) */#define PB_D5		PB(5)		/* Use D5 as PB(5) */#define PB_D6		PB(6)		/* Use D6 as PB(6) */#define PB_D7		PB(7)		/* Use D7 as PB(7) *//*  * Port C */#define PCDIR_ADDR	0xfffff410		/* Port C direction reg */#define PCDATA_ADDR	0xfffff411		/* Port C data register */#define PCSEL_ADDR	0xfffff413		/* Port C Select Register */#define PCDIR		BYTE_REF(PCDIR_ADDR)#define PCDATA		BYTE_REF(PCDATA_ADDR)#define PCSEL		BYTE_REF(PCSEL_ADDR)#define PC(x)           (1 << (x))#define PC_WE		PC(6)		/* Use WE    as PC(6) */#define PC_DTACK	PC(5)		/* Use DTACK as PC(5) */#define PC_IRQ7		PC(4)		/* Use IRQ7  as PC(4) */#define PC_LDS		PC(2)		/* Use LDS   as PC(2) */#define PC_UDS		PC(1)		/* Use UDS   as PC(1) */#define PC_MOCLK	PC(0)		/* Use MOCLK as PC(0) *//*  * Port D */#define PDDIR_ADDR	0xfffff418		/* Port D direction reg */#define PDDATA_ADDR	0xfffff419		/* Port D data register */#define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */#define PDPOL_ADDR	0xfffff41c		/* Port D Polarity Register */#define PDIRQEN_ADDR	0xfffff41d		/* Port D IRQ enable register */#define	PDIQEG_ADDR	0xfffff41f		/* Port D IRQ Edge Register */#define PDDIR		BYTE_REF(PDDIR_ADDR)#define PDDATA		BYTE_REF(PDDATA_ADDR)#define PDPUEN		BYTE_REF(PDPUEN_ADDR)#define	PDPOL		BYTE_REF(PDPOL_ADDR)#define PDIRQEN		BYTE_REF(PDIRQEN_ADDR)#define PDIQEG		BYTE_REF(PDIQEG_ADDR)#define PD(x)           (1 << (x))#define PD_KB(x)	PD(x)		/* This is specific for Port D only */#define PD_KB0		PD(0)	/* Use KB0 as PD(0) */#define PD_KB1		PD(1)	/* Use KB1 as PD(1) */#define PD_KB2		PD(2)	/* Use KB2 as PD(2) */#define PD_KB3		PD(3)	/* Use KB3 as PD(3) */#define PD_KB4		PD(4)	/* Use KB4 as PD(4) */#define PD_KB5		PD(5)	/* Use KB5 as PD(5) */#define PD_KB6		PD(6)	/* Use KB6 as PD(6) */#define PD_KB7		PD(7)	/* Use KB7 as PD(7) *//*  * Port E */#define PEDIR_ADDR	0xfffff420		/* Port E direction reg */#define PEDATA_ADDR	0xfffff421		/* Port E data register */#define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */#define PESEL_ADDR	0xfffff423		/* Port E Select Register */#define PEDIR		BYTE_REF(PEDIR_ADDR)#define PEDATA		BYTE_REF(PEDATA_ADDR)#define PEPUEN		BYTE_REF(PEPUEN_ADDR)#define PESEL		BYTE_REF(PESEL_ADDR)#define PE(x)           (1 << (x))#define PE_CSA1		PE(1)	/* Use CSA1 as PE(1) */#define PE_CSA2		PE(2)	/* Use CSA2 as PE(2) */#define PE_CSA3		PE(3)	/* Use CSA3 as PE(3) */#define PE_CSB0		PE(4)	/* Use CSB0 as PE(4) */#define PE_CSB1		PE(5)	/* Use CSB1 as PE(5) */#define PE_CSB2		PE(6)	/* Use CSB2 as PE(6) */#define PE_CSB3		PE(7)	/* Use CSB3 as PE(7) *//*  * Port F */#define PFDIR_ADDR	0xfffff428		/* Port F direction reg */#define PFDATA_ADDR	0xfffff429		/* Port F data register */#define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */#define PFSEL_ADDR	0xfffff42b		/* Port F Select Register */#define PFDIR		BYTE_REF(PFDIR_ADDR)#define PFDATA		BYTE_REF(PFDATA_ADDR)#define PFPUEN		BYTE_REF(PFPUEN_ADDR)#define PFSEL		BYTE_REF(PFSEL_ADDR)#define PF(x)           (1 << (x))#define PF_A(x)		PF((x) - 24)	/* This is Port F specific only */#define PF_A24		PF(0)	/* Use A24 as PF(0) */#define PF_A25		PF(1)	/* Use A25 as PF(1) */#define PF_A26		PF(2)	/* Use A26 as PF(2) */#define PF_A27		PF(3)	/* Use A27 as PF(3) */#define PF_A28		PF(4)	/* Use A28 as PF(4) */#define PF_A29		PF(5)	/* Use A29 as PF(5) */#define PF_A30		PF(6)	/* Use A30 as PF(6) */#define PF_A31		PF(7)	/* Use A31 as PF(7) *//*  * Port G */#define PGDIR_ADDR	0xfffff430		/* Port G direction reg */#define PGDATA_ADDR	0xfffff431		/* Port G data register */#define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */#define PGSEL_ADDR	0xfffff433		/* Port G Select Register */#define PGDIR		BYTE_REF(PGDIR_ADDR)#define PGDATA		BYTE_REF(PGDATA_ADDR)#define PGPUEN		BYTE_REF(PGPUEN_ADDR)#define PGSEL		BYTE_REF(PGSEL_ADDR)#define PG(x)           (1 << (x))#define PG_UART_TXD	PG(0)	/* Use UART_TXD as PG(0) */#define PG_UART_RXD	PG(1)	/* Use UART_RXD as PG(1) */#define PG_PWMOUT	PG(2)	/* Use PWMOUT   as PG(2) */#define PG_TOUT2	PG(3)   /* Use TOUT2    as PG(3) */#define PG_TIN2		PG(4)	/* Use TIN2     as PG(4) */#define PG_TOUT1	PG(5)   /* Use TOUT1    as PG(5) */#define PG_TIN1		PG(6)	/* Use TIN1     as PG(6) */#define PG_RTCOUT	PG(7)	/* Use RTCOUT   as PG(7) *//*  * Port J */#define PJDIR_ADDR	0xfffff438		/* Port J direction reg */#define PJDATA_ADDR	0xfffff439		/* Port J data register */#define PJSEL_ADDR	0xfffff43b		/* Port J Select Register */#define PJDIR		BYTE_REF(PJDIR_ADDR)#define PJDATA		BYTE_REF(PJDATA_ADDR)#define PJSEL		BYTE_REF(PJSEL_ADDR)#define PJ(x)           (1 << (x)) #define PJ_CSD3		PJ(7)	/* Use CSD3 as PJ(7) *//*  * Port K */#define PKDIR_ADDR	0xfffff440		/* Port K direction reg */#define PKDATA_ADDR	0xfffff441		/* Port K data register */#define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enable reg */#define PKSEL_ADDR	0xfffff443		/* Port K Select Register */#define PKDIR		BYTE_REF(PKDIR_ADDR)#define PKDATA		BYTE_REF(PKDATA_ADDR)#define PKPUEN		BYTE_REF(PKPUEN_ADDR)#define PKSEL		BYTE_REF(PKSEL_ADDR)#define PK(x)           (1 << (x))/*  * Port M */#define PMDIR_ADDR	0xfffff438		/* Port M direction reg */#define PMDATA_ADDR	0xfffff439		/* Port M data register */#define PMPUEN_ADDR	0xfffff43a		/* Port M Pull-Up enable reg */#define PMSEL_ADDR	0xfffff43b		/* Port M Select Register */#define PMDIR		BYTE_REF(PMDIR_ADDR)#define PMDATA		BYTE_REF(PMDATA_ADDR)#define PMPUEN		BYTE_REF(PMPUEN_ADDR)#define PMSEL		BYTE_REF(PMSEL_ADDR)#define PM(x)           (1 << (x))/********** * * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) * **********//* * PWM Control Register  */#define PWMC_ADDR	0xfffff500#define PWMC		WORD_REF(PWMC_ADDR)#define PWMC_CLKSEL_MASK	0x0007	/* Clock Selection */#define PWMC_CLKSEL_SHIFT	0#define PWMC_PWMEN		0x0010	/* Enable PWM */#define PMNC_POL		0x0020	/* PWM Output Bit Polarity */#define PWMC_PIN		0x0080	/* Current PWM output pin status */#define PWMC_LOAD		0x0100	/* Force a new period */#define PWMC_IRQEN		0x4000	/* Interrupt Request Enable */#define PWMC_CLKSRC		0x8000	/* Clock Source Select *//* 'EZ328-compatible definitions */#define PWMC_EN	PWMC_PWMEN/* * PWM Period Register */#define PWMP_ADDR	0xfffff502#define PWMP		WORD_REF(PWMP_ADDR)/*  * PWM Width Register  */#define PWMW_ADDR	0xfffff504#define PWMW		WORD_REF(PWMW_ADDR)/* * PWM Counter Register */#define PWMCNT_ADDR	0xfffff506#define PWMCNT		WORD_REF(PWMCNT_ADDR)/********** * * 0xFFFFF6xx -- General-Purpose Timers * **********//*  * Timer Unit 1 and 2 Control Registers */#define TCTL1_ADDR	0xfffff600#define TCTL1		WORD_REF(TCTL1_ADDR)#define TCTL2_ADDR	0xfffff60c#define TCTL2		WORD_REF(TCTL2_ADDR)#define	TCTL_TEN		0x0001	/* Timer Enable  */#define TCTL_CLKSOURCE_MASK 	0x000e	/* Clock Source: */#define   TCTL_CLKSOURCE_STOP	   0x0000	/* Stop count (disabled)    */#define   TCTL_CLKSOURCE_SYSCLK	   0x0002	/* SYSCLK to prescaler      */#define   TCTL_CLKSOURCE_SYSCLK_16 0x0004	/* SYSCLK/16 to prescaler   */#define   TCTL_CLKSOURCE_TIN	   0x0006	/* TIN to prescaler         */#define   TCTL_CLKSOURCE_32KHZ	   0x0008	/* 32kHz clock to prescaler */#define TCTL_IRQEN		0x0010	/* IRQ Enable    */#define TCTL_OM			0x0020	/* Output Mode   */#define TCTL_CAP_MASK		0x00c0	/* Capture Edge: */#define	  TCTL_CAP_RE		0x0040		/* Capture on rizing edge   */#define   TCTL_CAP_FE		0x0080		/* Capture on falling edge  */#define TCTL_FRR		0x0010	/* Free-Run Mode *//* 'EZ328-compatible definitions */#define TCTL_ADDR	TCTL1_ADDR#define TCTL		TCTL1/* * Timer Unit 1 and 2 Prescaler Registers */#define TPRER1_ADDR	0xfffff602#define TPRER1		WORD_REF(TPRER1_ADDR)#define TPRER2_ADDR	0xfffff60e#define TPRER2		WORD_REF(TPRER2_ADDR)/* 'EZ328-compatible definitions */#define TPRER_ADDR	TPRER1_ADDR#define TPRER		TPRER1/* * Timer Unit 1 and 2 Compare Registers */#define TCMP1_ADDR	0xfffff604#define TCMP1		WORD_REF(TCMP1_ADDR)#define TCMP2_ADDR	0xfffff610#define TCMP2		WORD_REF(TCMP2_ADDR)/* 'EZ328-compatible definitions */#define TCMP_ADDR	TCMP1_ADDR#define TCMP		TCMP1/* * Timer Unit 1 and 2 Capture Registers */#define TCR1_ADDR	0xfffff606#define TCR1		WORD_REF(TCR1_ADDR)#define TCR2_ADDR	0xfffff612#define TCR2		WORD_REF(TCR2_ADDR)/* 'EZ328-compatible definitions */#define TCR_ADDR	TCR1_ADDR#define TCR		TCR1/* * Timer Unit 1 and 2 Counter Registers */#define TCN1_ADDR	0xfffff608#define TCN1		WORD_REF(TCN1_ADDR)#define TCN2_ADDR	0xfffff614#define TCN2		WORD_REF(TCN2_ADDR)/* 'EZ328-compatible definitions */#define TCN_ADDR	TCN1_ADDR#define TCN		TCN/* * Timer Unit 1 and 2 Status Registers */#define TSTAT1_ADDR	0xfffff60a#define TSTAT1		WORD_REF(TSTAT1_ADDR)#define TSTAT2_ADDR	0xfffff616#define TSTAT2		WORD_REF(TSTAT2_ADDR)#define TSTAT_COMP	0x0001		/* Compare Event occurred */#define TSTAT_CAPT	0x0001		/* Capture Event occurred *//* 'EZ328-compatible definitions */#define TSTAT_ADDR	TSTAT1_ADDR#define TSTAT		TSTAT1/* * Watchdog Compare Register  */#define WRR_ADDR	0xfffff61a#define WRR		WORD_REF(WRR_ADDR)/* * Watchdog Counter Register  */#define WCN_ADDR	0xfffff61c#define WCN		WORD_REF(WCN_ADDR)/* * Watchdog Control and Status Register */#define WCSR_ADDR	0xfffff618#define WCSR		WORD_REF(WCSR_ADDR)#define WCSR_WDEN	0x0001	/* Watchdog Enable */#define WCSR_FI		0x0002	/* Forced Interrupt (instead of SW reset)*/#define WCSR_WRST	0x0004	/* Watchdog Reset *//********** * * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS) * **********//* * SPI Slave Register */#define SPISR_ADDR	0xfffff700#define SPISR		WORD_REF(SPISR_ADDR)#define SPISR_DATA_ADDR	0xfffff701#define SPISR_DATA	BYTE_REF(SPISR_DATA_ADDR)#define SPISR_DATA_MASK	 0x00ff	/* Shifted data from the external device */#define SPISR_DATA_SHIFT 0#define SPISR_SPISEN	 0x0100	/* SPIS module enable */#define SPISR_POL	 0x0200	/* SPSCLK polarity control */#define SPISR_PHA	 0x0400	/* Phase relationship between SPSCLK & SPSRxD */#define SPISR_OVWR	 0x0800	/* Data buffer has been overwritten */#define SPISR_DATARDY	 0x1000	/* Data ready */#define SPISR_ENPOL	 0x2000	/* Enable Polarity */#define SPISR_IRQEN	 0x4000	/* SPIS IRQ Enable */#define SPISR_SPISIRQ	 0x8000	/* SPIS IRQ posted *//********** * * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) * **********//* * SPIM Data Register */#define SPIMDATA_ADDR	0xfffff800#define SPIMDATA	WORD_REF(SPIMDATA_ADDR)/* * SPIM Control/Status Register */#define SPIMCONT_ADDR	0xfffff802#define SPIMCONT	WORD_REF(SPIMCONT_ADDR)#define SPIMCONT_BIT_COUNT_MASK	 0x000f	/* Transfer Length in Bytes */#define SPIMCONT_BIT_COUNT_SHIFT 0#define SPIMCONT_POL		 0x0010	/* SPMCLK Signel Polarity */#define	SPIMCONT_PHA		 0x0020	/* Clock/Data phase relationship */
mc68328.h - 源码说明

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