pic.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 452 行 · 第 1/2 页

#define PIC_ISR_XTALK_ERROR           \
                (PIC_ISR_XREAD_REQ_TIMEOUT|PIC_ISR_XREQ_FIFO_OFLOW| \
                 PIC_ISR_UNSUPPORTED_XOP|PIC_ISR_INVLD_ADDR|        \
                 PIC_ISR_REQ_XTLK_ERR|PIC_ISR_RESP_XTLK_ERR|        \
                 PIC_ISR_BAD_XREQ_PKT|PIC_ISR_BAD_XRESP_PKT|        \
                 PIC_ISR_UNEXP_RESP)

#define PIC_ISR_ERRORS                \
                (PIC_ISR_LINK_ERROR|PIC_ISR_PCIBUS_ERROR|           \
                 PIC_ISR_XTALK_ERROR|                                 \
                 PIC_ISR_PMU_PAGE_FAULT|PIC_ISR_INT_RAM_PERR)

/*
 * PIC RESET INTR register      offset 0x00000110
 */

#define PIC_IRR_ALL_CLR                 0xffffffffffffffff

/*
 * PIC PCI Host Intr Addr       offset 0x00000130 - 0x00000168
 */
#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFF
#define PIC_HOST_INTR_FLD_SHFT          48
#define PIC_HOST_INTR_FLD               (0xFFull << PIC_HOST_INTR_FLD_SHFT)


/*
 * PIC MMR structure mapping
 */

/* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
 * of a 64-bit register.  When writing PIC registers, always write the 
 * entire 64 bits.
 */

typedef volatile struct pic_s {

    /* 0x000000-0x00FFFF -- Local Registers */

    /* 0x000000-0x000057 -- Standard Widget Configuration */
    picreg_t		p_wid_id;			/* 0x000000 */
    picreg_t		p_wid_stat;			/* 0x000008 */
    picreg_t		p_wid_err_upper;		/* 0x000010 */
    picreg_t		p_wid_err_lower;		/* 0x000018 */
    #define p_wid_err p_wid_err_lower
    picreg_t		p_wid_control;			/* 0x000020 */
    picreg_t		p_wid_req_timeout;		/* 0x000028 */
    picreg_t		p_wid_int_upper;		/* 0x000030 */
    picreg_t		p_wid_int_lower;		/* 0x000038 */
    #define p_wid_int p_wid_int_lower
    picreg_t		p_wid_err_cmdword;		/* 0x000040 */
    picreg_t		p_wid_llp;			/* 0x000048 */
    picreg_t		p_wid_tflush;			/* 0x000050 */

    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
    picreg_t		p_wid_aux_err;			/* 0x000058 */
    picreg_t		p_wid_resp_upper;		/* 0x000060 */
    picreg_t		p_wid_resp_lower;		/* 0x000068 */
    #define p_wid_resp p_wid_resp_lower
    picreg_t		p_wid_tst_pin_ctrl;		/* 0x000070 */
    picreg_t		p_wid_addr_lkerr;		/* 0x000078 */

    /* 0x000080-0x00008F -- PMU & MAP */
    picreg_t		p_dir_map;			/* 0x000080 */
    picreg_t		_pad_000088;			/* 0x000088 */

    /* 0x000090-0x00009F -- SSRAM */
    picreg_t		p_map_fault;			/* 0x000090 */
    picreg_t		_pad_000098;			/* 0x000098 */

    /* 0x0000A0-0x0000AF -- Arbitration */
    picreg_t		p_arb;				/* 0x0000A0 */
    picreg_t		_pad_0000A8;			/* 0x0000A8 */

    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
    picreg_t		p_ate_parity_err;		/* 0x0000B0 */
    picreg_t		_pad_0000B8;			/* 0x0000B8 */

    /* 0x0000C0-0x0000FF -- PCI/GIO */
    picreg_t		p_bus_timeout;			/* 0x0000C0 */
    picreg_t		p_pci_cfg;			/* 0x0000C8 */
    picreg_t		p_pci_err_upper;		/* 0x0000D0 */
    picreg_t		p_pci_err_lower;		/* 0x0000D8 */
    #define p_pci_err p_pci_err_lower
    picreg_t		_pad_0000E0[4];			/* 0x0000{E0..F8} */

    /* 0x000100-0x0001FF -- Interrupt */
    picreg_t		p_int_status;			/* 0x000100 */
    picreg_t		p_int_enable;			/* 0x000108 */
    picreg_t		p_int_rst_stat;			/* 0x000110 */
    picreg_t		p_int_mode;			/* 0x000118 */
    picreg_t		p_int_device;			/* 0x000120 */
    picreg_t		p_int_host_err;			/* 0x000128 */
    picreg_t		p_int_addr[8];			/* 0x0001{30,,,68} */
    picreg_t		p_err_int_view;			/* 0x000170 */
    picreg_t		p_mult_int;			/* 0x000178 */
    picreg_t		p_force_always[8];		/* 0x0001{80,,,B8} */
    picreg_t		p_force_pin[8];			/* 0x0001{C0,,,F8} */

    /* 0x000200-0x000298 -- Device */
    picreg_t		p_device[4];			/* 0x0002{00,,,18} */
    picreg_t		_pad_000220[4];			/* 0x0002{20,,,38} */
    picreg_t		p_wr_req_buf[4];		/* 0x0002{40,,,58} */
    picreg_t		_pad_000260[4];			/* 0x0002{60,,,78} */
    picreg_t		p_rrb_map[2];			/* 0x0002{80,,,88} */
    #define p_even_resp p_rrb_map[0]			/* 0x000280 */
    #define p_odd_resp  p_rrb_map[1]			/* 0x000288 */
    picreg_t		p_resp_status;			/* 0x000290 */
    picreg_t		p_resp_clear;			/* 0x000298 */

    picreg_t		_pad_0002A0[12];		/* 0x0002{A0..F8} */

    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
    struct {
	picreg_t	upper;				/* 0x0003{00,,,F0} */
	picreg_t	lower;				/* 0x0003{08,,,F8} */
    } p_buf_addr_match[16];

    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
    struct {
	picreg_t	flush_w_touch;			/* 0x000{400,,,5C0} */
	picreg_t	flush_wo_touch;			/* 0x000{408,,,5C8} */
	picreg_t	inflight;			/* 0x000{410,,,5D0} */
	picreg_t	prefetch;			/* 0x000{418,,,5D8} */
	picreg_t	total_pci_retry;		/* 0x000{420,,,5E0} */
	picreg_t	max_pci_retry;			/* 0x000{428,,,5E8} */
	picreg_t	max_latency;			/* 0x000{430,,,5F0} */
	picreg_t	clear_all;			/* 0x000{438,,,5F8} */
    } p_buf_count[8];

    
    /* 0x000600-0x0009FF -- PCI/X registers */
    picreg_t		p_pcix_bus_err_addr;		/* 0x000600 */
    picreg_t		p_pcix_bus_err_attr;		/* 0x000608 */
    picreg_t		p_pcix_bus_err_data;		/* 0x000610 */
    picreg_t		p_pcix_pio_split_addr;		/* 0x000618 */
    picreg_t		p_pcix_pio_split_attr;		/* 0x000620 */
    picreg_t		p_pcix_dma_req_err_attr;	/* 0x000628 */
    picreg_t		p_pcix_dma_req_err_addr;	/* 0x000630 */
    picreg_t		p_pcix_timeout;			/* 0x000638 */

    picreg_t		_pad_000640[120];		/* 0x000{640,,,9F8} */

    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
    struct {
	picreg_t	p_buf_addr;			/* 0x000{A00,,,AF0} */
	picreg_t	p_buf_attr;			/* 0X000{A08,,,AF8} */
    } p_pcix_read_buf_64[16];

    struct {
	picreg_t	p_buf_addr;			/* 0x000{B00,,,BE0} */
	picreg_t	p_buf_attr;			/* 0x000{B08,,,BE8} */
	picreg_t	p_buf_valid;			/* 0x000{B10,,,BF0} */
	picreg_t	__pad1;				/* 0x000{B18,,,BF8} */
    } p_pcix_write_buf_64[8];

    /* End of Local Registers -- Start of Address Map space */

    char		_pad_000c00[0x010000 - 0x000c00];

    /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
    picate_t		p_int_ate_ram[1024];		/* 0x010000-0x011fff */

    /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
    picate_t		p_int_ate_ram_mp[1024];		/* 0x012000-0x013fff */

    char		_pad_014000[0x18000 - 0x014000];

    /* 0x18000-0x197F8 -- PIC Write Request Ram */
    picreg_t		p_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
    picreg_t		p_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
    picreg_t		p_wr_req_parity[256];		/* 0x19000 - 0x197F8 */

    char		_pad_019800[0x20000 - 0x019800];

    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
    union {
	uint8_t		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
	uint16_t	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
	uint32_t	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
	uint64_t	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
	union {
	    uint8_t	c[0x100 / 1];
	    uint16_t	s[0x100 / 2];
	    uint32_t	l[0x100 / 4];
	    uint64_t	d[0x100 / 8];
	} f[8];
    } p_type0_cfg_dev[8];				/* 0x02{0000,,,7FFF} */

    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
    union {
	uint8_t		c[0x1000 / 1];			/* 0x028000-0x029000 */
	uint16_t	s[0x1000 / 2];			/* 0x028000-0x029000 */
	uint32_t	l[0x1000 / 4];			/* 0x028000-0x029000 */
	uint64_t	d[0x1000 / 8];			/* 0x028000-0x029000 */
	union {
	    uint8_t	c[0x100 / 1];
	    uint16_t	s[0x100 / 2];
	    uint32_t	l[0x100 / 4];
	    uint64_t	d[0x100 / 8];
	} f[8];
    } p_type1_cfg;					/* 0x028000-0x029000 */

    char		_pad_029000[0x030000-0x029000];

    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
    union {
	uint8_t		c[8 / 1];
	uint16_t	s[8 / 2];
	uint32_t	l[8 / 4];
	uint64_t	d[8 / 8];
    } p_pci_iack;					/* 0x030000-0x030007 */

    char		_pad_030007[0x040000-0x030008];

    /* 0x040000-0x030007 -- PCIX Special Cycle */
    union {
	uint8_t		c[8 / 1];
	uint16_t	s[8 / 2];
	uint32_t	l[8 / 4];
	uint64_t	d[8 / 8];
    } p_pcix_cycle;					/* 0x040000-0x040007 */
} pic_t;

#endif                          /* _ASM_IA64_SN_PCI_PIC_H */