mv643xx.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 1,040 行 · 第 1/5 页
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#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8/****************************************//* PCI Configuration Access Registers *//****************************************/#define MV64340_PCI_0_CONFIG_ADDR 0xcf8#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc#define MV64340_PCI_1_CONFIG_ADDR 0xc78#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4/****************************************//* PCI Error Report Registers *//****************************************/#define MV64340_PCI_0_SERR_MASK 0xc28#define MV64340_PCI_1_SERR_MASK 0xca8#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8#define MV64340_PCI_0_ERROR_COMMAND 0x1d50#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0#define MV64340_PCI_0_ERROR_CAUSE 0x1d58#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8#define MV64340_PCI_0_ERROR_MASK 0x1d5c#define MV64340_PCI_1_ERROR_MASK 0x1ddc/****************************************//* PCI Debug Registers *//****************************************/#define MV64340_PCI_0_MMASK 0X1D24#define MV64340_PCI_1_MMASK 0X1DA4/*********************************************//* PCI Configuration, Function 0, Registers *//*********************************************/#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000#define MV64340_PCI_STATUS_AND_COMMAND 0x004#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C /* capability list */#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044#define MV64340_PCI_VPD_ADDR 0x048#define MV64340_PCI_VPD_DATA 0x04c#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c#define MV64340_PCI_X_COMMAND 0x060#define MV64340_PCI_X_STATUS 0x064#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068/***********************************************//* PCI Configuration, Function 1, Registers *//***********************************************/#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124/***********************************************//* PCI Configuration, Function 2, Registers *//***********************************************/#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224/***********************************************//* PCI Configuration, Function 3, Registers *//***********************************************/#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224/***********************************************//* PCI Configuration, Function 4, Registers *//***********************************************/#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424/****************************************//* Messaging Unit Registers (I20) *//****************************************/#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44⌨️ 快捷键说明
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