gt64120.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 431 行 · 第 1/2 页
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431 行
#define GT_SDRAM_B0_CASLAT_SHF 0#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)#define GT_SDRAM_B0_CASLAT_2 1#define GT_SDRAM_B0_CASLAT_3 2#define GT_SDRAM_B0_FTDIS_SHF 2#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK#define GT_SDRAM_B0_SRASPRCHG_SHF 3#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK#define GT_SDRAM_B0_SRASPRCHG_2 0#define GT_SDRAM_B0_SRASPRCHG_3 1#define GT_SDRAM_B0_B0COMPAB_SHF 4#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK#define GT_SDRAM_B0_64BITINT_SHF 5#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK#define GT_SDRAM_B0_64BITINT_2 0#define GT_SDRAM_B0_64BITINT_4 1#define GT_SDRAM_B0_BW_SHF 6#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK#define GT_SDRAM_B0_BW_32 0#define GT_SDRAM_B0_BW_64 1#define GT_SDRAM_B0_BLODD_SHF 7#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK#define GT_SDRAM_B0_PAR_SHF 8#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK#define GT_SDRAM_B0_BYPASS_SHF 9#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK#define GT_SDRAM_B0_SRAS2SCAS_SHF 10#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK#define GT_SDRAM_B0_SRAS2SCAS_2 0#define GT_SDRAM_B0_SRAS2SCAS_3 1#define GT_SDRAM_B0_SIZE_SHF 11#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK#define GT_SDRAM_B0_SIZE_16M 0#define GT_SDRAM_B0_SIZE_64M 1#define GT_SDRAM_B0_EXTPAR_SHF 12#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK#define GT_SDRAM_B0_BLEN_SHF 13#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK#define GT_SDRAM_B0_BLEN_8 0#define GT_SDRAM_B0_BLEN_4 1#define GT_SDRAM_CFG_REFINT_SHF 0#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK#define GT_SDRAM_CFG_RMW_SHF 15#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK#define GT_SDRAM_CFG_NONSTAGREF_SHF 16#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK#define GT_SDRAM_CFG_DUPCNTL_SHF 19#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK#define GT_SDRAM_CFG_DUPBA_SHF 20#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK#define GT_SDRAM_CFG_DUPEOT0_SHF 21#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK#define GT_SDRAM_CFG_DUPEOT1_SHF 22#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK#define GT_SDRAM_OPMODE_OP_SHF 0#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)#define GT_SDRAM_OPMODE_OP_NORMAL 0#define GT_SDRAM_OPMODE_OP_NOP 1#define GT_SDRAM_OPMODE_OP_PRCHG 2#define GT_SDRAM_OPMODE_OP_MODE 3#define GT_SDRAM_OPMODE_OP_CBR 4#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK#define GT_PCI0_BARE_SWSCS32DIS_SHF 1#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK#define GT_PCI0_BARE_SWSCS10DIS_SHF 2#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK#define GT_PCI0_BARE_INTIODIS_SHF 3#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK#define GT_PCI0_BARE_INTMEMDIS_SHF 4#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK#define GT_PCI0_BARE_CS20DIS_SHF 6#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK#define GT_PCI0_BARE_SCS32DIS_SHF 7#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK#define GT_PCI0_BARE_SCS10DIS_SHF 8#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK#define GT_INTRCAUSE_MASABORT0_SHF 18#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK#define GT_INTRCAUSE_TARABORT0_SHF 19#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK#define GT_PCI0_CFGADDR_REGNUM_SHF 2#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)#define GT_PCI0_CFGADDR_DEVNUM_SHF 11#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)#define GT_PCI0_CFGADDR_BUSNUM_SHF 16#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK#define GT_PCI0_CMD_MBYTESWAP_SHF 0#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK#define GT_PCI0_CMD_MWORDSWAP_SHF 10#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK#define GT_PCI0_CMD_SBYTESWAP_SHF 16#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK#define GT_PCI0_CMD_SWORDSWAP_SHF 11#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK/* * Misc */#define GT_DEF_PCI0_IO_BASE 0x10000000UL#define GT_DEF_PCI0_IO_SIZE 0x02000000UL#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL#define GT_DEF_BASE 0x14000000UL#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */#define GT_LATTIM_MIN 6 /* Minimum lat *//* * The gt64120_dep.h file must define the following macros * * GT_READ(ofs, data_pointer) * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit * * TIMER - gt64120 timer irq, temporary solution until * full gt64120 cascade interrupt support is in place */#include <mach-gt64120.h>/* * Because of an error/peculiarity in the Galileo chip, we need to swap the * bytes when running bigendian. We also provide non-swapping versions. */#define __GT_READ(ofs) \ (*(volatile u32 *)(GT64120_BASE+(ofs)))#define __GT_WRITE(ofs, data) \ do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))#endif /* _ASM_GT64120_H */⌨️ 快捷键说明
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