omap24xxfb.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 451 行 · 第 1/2 页

#define DISPC_CONTROL_TFTDITHERENABLE			(1 <<  7)
#define DISPC_CONTROL_GODIGITAL				(1 <<  6)
#define DISPC_CONTROL_GOLCD				(1 <<  5)
#define DISPC_CONTROL_M8B				(1 <<  4)
#define DISPC_CONTROL_STNTFT				(1 <<  3)
#define DISPC_CONTROL_MONOCOLOR				(1 <<  2)
#define DISPC_CONTROL_DIGITALENABLE			(1 <<  1)
#define DISPC_CONTROL_LCDENABLE				(1 <<  0)

#define DISPC_CONFIG_TCKDIGSELECTION			(1 << 13)
#define DISPC_CONFIG_TCKDIGENABLE			(1 << 12)
#define DISPC_CONFIG_TCKLCDSELECTION			(1 << 11)
#define DISPC_CONFIG_TCKLCDENABLE			(1 << 10)
#define DISPC_CONFIG_FUNCGATED				(1 <<  9)
#define DISPC_CONFIG_ACBIASGATED			(1 <<  8)
#define DISPC_CONFIG_VSYNCGATED				(1 <<  7)
#define DISPC_CONFIG_HSYNCGATED				(1 <<  6)
#define DISPC_CONFIG_PIXELCLOCKGATED			(1 <<  5)
#define DISPC_CONFIG_PIXELDATAGATED			(1 <<  4)
#define DISPC_CONFIG_PALETTEGAMMATABLE			(1 <<  3)
#define DISPC_CONFIG_LOADMODE_FRDATLEFR			(1 <<  2)
#define DISPC_CONFIG_LOADMODE_PGTABUSETB		(1 <<  1)
#define DISPC_CONFIG_PIXELGATED				(1 <<  0)

#define DISPC_CAPABLE_GFXGAMMATABLECAPABLE		(1 <<  9)
#define DISPC_CAPABLE_GFXLAYERCAPABLE			(1 <<  8)
#define DISPC_CAPABLE_GFXTRANSDSTCAPABLE		(1 <<  7)
#define DISPC_CAPABLE_STNDITHERINGCAPABLE		(1 <<  6)
#define DISPC_CAPABLE_TFTDITHERINGCAPABLE		(1 <<  5)
#define DISPC_CAPABLE_VIDTRANSSRCCAPABLE		(1 <<  4)
#define DISPC_CAPABLE_VIDLAYERCAPABLE			(1 <<  3)
#define DISPC_CAPABLE_VIDVERTFIRCAPABLE			(1 <<  2)
#define DISPC_CAPABLE_VIDHORFIRCAPABLE			(1 <<  1)
#define DISPC_CAPABLE_VIDCAPABLE			(1 <<  0)

#define DISPC_POL_FREQ_ONOFF				(1 << 17)
#define DISPC_POL_FREQ_RF				(1 << 16)
#define DISPC_POL_FREQ_IEO				(1 << 15)
#define DISPC_POL_FREQ_IPC				(1 << 14)
#define DISPC_POL_FREQ_IHS				(1 << 13)
#define DISPC_POL_FREQ_IVS				(1 << 12)
#define DISPC_POL_FREQ_ACBI				(15 << 8)
#define DISPC_POL_FREQ_ACBI_SHIFT			8
#define DISPC_POL_FREQ_ACB				0xFF
#define DISPC_POL_FREQ_ACB_SHIFT			0

#define DISPC_TIMING_H_HBP				(0xFF << 20)
#define DISPC_TIMING_H_HBP_SHIFT			20
#define DISPC_TIMING_H_HFP				(0xFF << 8)
#define DISPC_TIMING_H_HFP_SHIFT			8
#define DISPC_TIMING_H_HSW				(0x3F << 0)
#define DISPC_TIMING_H_HSW_SHIFT			0

#define DISPC_TIMING_V_VBP				(0xFF << 20)
#define DISPC_TIMING_V_VBP_SHIFT			20
#define DISPC_TIMING_V_VFP				(0xFF << 8)
#define DISPC_TIMING_V_VFP_SHIFT			8
#define DISPC_TIMING_V_VSW				(0x3F << 0)
#define DISPC_TIMING_V_VSW_SHIFT			0

#define DISPC_DIVISOR_LCD				(0xFF << 16)
#define DISPC_DIVISOR_LCD_SHIFT				16
#define DISPC_DIVISOR_PCD				0xFF
#define DISPC_DIVISOR_PCD_SHIFT				0

#define DISPC_SIZE_LCD_LPP				(0x7FF << 16)
#define DISPC_SIZE_LCD_LPP_SHIFT			16
#define DISPC_SIZE_LCD_PPL				0x7FF
#define DISPC_SIZE_LCD_PPL_SHIFT			0

#define DISPC_SIZE_DIG_LPP				(0x7FF << 16)
#define DISPC_SIZE_DIG_LPP_SHIFT			16
#define DISPC_SIZE_DIG_PPL				0x7FF
#define DISPC_SIZE_DIG_PPL_SHIFT			0

#define DISPC_GFX_POSITION_GFXPOSY			(0x7FF << 16)
#define DISPC_GFX_POSITION_GFXPOSY_SHIFT		16
#define DISPC_GFX_POSITION_GFXPOSX			0x7FF
#define DISPC_GFX_POSITION_GFXPOSX_SHIFT		0

#define DISPC_GFX_SIZE_GFXSIZEY				(0x7FF << 16)
#define DISPC_GFX_SIZE_GFXSIZEY_SHIFT			16
#define DISPC_GFX_SIZE_GFXSIZEX				0x7FF
#define DISPC_GFX_SIZE_GFXSIZEX_SHIFT			0

#define DISPC_GFX_ATTRIBUTES_GFXENDIANNESS		(1 << 10)
#define DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE		(1 <<  9)
#define DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT		(1 <<  8)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE		(3 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST4X32	(0 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST8X32	(1 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST16X32	(2 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE	(1 <<  5)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT			(15 << 1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1		(0 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2		(1 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4		(2 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8		(3 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12		(4 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16		(6 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24		(8 <<  1)
#define DISPC_GFX_ATTRIBUTES_ENABLE			(1 <<  0)

#define DISPC_GFX_FIFO_THRESHOLD_HIGH			(0x1FF << 16)
#define DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT		16
#define DISPC_GFX_FIFO_THRESHOLD_LOW			0x1FF
#define DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT		0

#define DISPC_VID_ATTRIBUTES_ENABLE			(1 <<  0)

struct omap24xx_dispc_regs {
	u32 revision;			/* 0x000 */
	u32 res1[3];
	u32 sysconfig;			/* 0x010 */
	u32 sysstatus;			/* 0x014 */
	u32 irqstatus;			/* 0x018 */
	u32 irqenable;			/* 0x01C */
	u32 res2[8];
	u32 control;			/* 0x040 */
	u32 config;			/* 0x044 */
	u32 capable;			/* 0x048 */
	u32 default_color0;		/* 0x04C */
	u32 default_color1;		/* 0x050 */
	u32 trans_color0;		/* 0x054 */
	u32 trans_color1;		/* 0x058 */
	u32 line_status;		/* 0x05C */
	u32 line_number;		/* 0x060 */
	u32 timing_h;			/* 0x064 */
	u32 timing_v;			/* 0x068 */
	u32 pol_freq;			/* 0x06C */
	u32 divisor;			/* 0x070 */
	u32 res3[1];
	u32 size_dig;			/* 0x078 */
	u32 size_lcd;			/* 0x07C */
	u32 gfx_ba0;			/* 0x080 */
	u32 gfx_ba1;			/* 0x084 */
	u32 gfx_position;		/* 0x088 */
	u32 gfx_size;			/* 0x08C */
	u32 res4[4];
	u32 gfx_attributes;		/* 0x0A0 */
	u32 gfx_fifo_threshold;		/* 0x0A4 */
	u32 gfx_fifo_size;		/* 0x0A8 */
	u32 gfx_row_inc;		/* 0x0AC */
	u32 gfx_pixel_inc;		/* 0x0B0 */
	u32 gfx_window_skip;		/* 0x0B4 */
	u32 gfx_table_ba;		/* 0x0B8 */
	u32 vid1_ba0;			/* 0x0BC */
	u32 vid1_ba1;			/* 0x0C0 */
	u32 vid1_position;		/* 0x0C4 */
	u32 vid1_size;			/* 0x0C8 */
	u32 vid1_attributes;		/* 0x0CC */
	u32 vid1_fifo_threshold;	/* 0x0D0 */
	u32 vid1_fifo_size;		/* 0x0D4 */
	u32 vid1_row_inc;		/* 0x0D8 */
	u32 vid1_pixel_inc;		/* 0x0DC */
	u32 vid1_fir;			/* 0x0E0 */
	u32 vid1_picture_size;		/* 0x0E4 */
	u32 vid1_accu0;			/* 0x0E8 */
	u32 vid1_accu1;			/* 0x0EC */
	u32 vid1_fir_coef_h0;		/* 0x0F0 */
	u32 vid1_fir_coef_hv0;		/* 0x0F4 */
	u32 vid1_fir_coef_h1;		/* 0x0F8 */
	u32 vid1_fir_coef_hv1;		/* 0x0FC */
	u32 vid1_fir_coef_h2;		/* 0x100 */
	u32 vid1_fir_coef_hv2;		/* 0x104 */
	u32 vid1_fir_coef_h3;		/* 0x108 */
	u32 vid1_fir_coef_hv3;		/* 0x10C */
	u32 vid1_fir_coef_h4;		/* 0x110 */
	u32 vid1_fir_coef_hv4;		/* 0x114 */
	u32 vid1_fir_coef_h5;		/* 0x118 */
	u32 vid1_fir_coef_hv5;		/* 0x11C */
	u32 vid1_fir_coef_h6;		/* 0x120 */
	u32 vid1_fir_coef_hv6;		/* 0x124 */
	u32 vid1_fir_coef_h7;		/* 0x128 */
	u32 vid1_fir_coef_hv7;		/* 0x12C */
	u32 vid1_conv_coef0;		/* 0x130 */
	u32 vid1_conv_coef1;		/* 0x134 */
	u32 vid1_conv_coef2;		/* 0x138 */
	u32 vid1_conv_coef3;		/* 0x13C */
	u32 vid1_conv_coef4;		/* 0x140 */
	u32 res5[2];
	u32 vid2_ba0;			/* 0x14C */
	u32 vid2_ba1;			/* 0x150 */
	u32 vid2_position;		/* 0x154 */
	u32 vid2_size;			/* 0x158 */
	u32 vid2_attributes;		/* 0x15C */
	u32 vid2_fifo_threshold;	/* 0x160 */
	u32 vid2_fifo_size;		/* 0x164 */
	u32 vid2_row_inc;		/* 0x168 */
	u32 vid2_pixel_inc;		/* 0x16C */
	u32 vid2_fir;			/* 0x170 */
	u32 vid2_picture_size;		/* 0x174 */
	u32 vid2_accu0;			/* 0x178 */
	u32 vid2_accu1;			/* 0x17C */
	u32 vid2_fir_coef_h0;		/* 0x180 */
	u32 vid2_fir_coef_hv0;		/* 0x184 */
	u32 vid2_fir_coef_h1;		/* 0x188 */
	u32 vid2_fir_coef_hv1;		/* 0x18C */
	u32 vid2_fir_coef_h2;		/* 0x190 */
	u32 vid2_fir_coef_hv2;		/* 0x194 */
	u32 vid2_fir_coef_h3;		/* 0x198 */
	u32 vid2_fir_coef_hv3;		/* 0x19C */
	u32 vid2_fir_coef_h4;		/* 0x1A0 */
	u32 vid2_fir_coef_hv4;		/* 0x1A4 */
	u32 vid2_fir_coef_h5;		/* 0x1A8 */
	u32 vid2_fir_coef_hv5;		/* 0x1AC */
	u32 vid2_fir_coef_h6;		/* 0x1B0 */
	u32 vid2_fir_coef_hv6;		/* 0x1B4 */
	u32 vid2_fir_coef_h7;		/* 0x1B8 */
	u32 vid2_fir_coef_hv7;		/* 0x1BC */
	u32 vid2_conv_coef0;		/* 0x1C0 */
	u32 vid2_conv_coef1;		/* 0x1C4 */
	u32 vid2_conv_coef2;		/* 0x1C8 */
	u32 vid2_conv_coef3;		/* 0x1CC */
	u32 vid2_conv_coef4;		/* 0x1D0 */
	u32 data_cycle1;		/* 0x1D4 */
	u32 data_cycle2;		/* 0x1D8 */
	u32 data_cycle3;		/* 0x1DC */
};

/* define the custom FBIO_WAITFORVSYNC ioctl */
#define FBIO_WAITFORVSYNC	_IOW('F', 0x20, u_int32_t)

#endif	/* ifndef OMAP24XXFB_H */