omap24xxfb.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 1,697 行 · 第 1/4 页

	return (ctrl & mask);
}

/* Enable the display controller */
static void
omap24xxfb_enable(const struct omap24xxfb_info *oinfo, 
		const struct omap24xx_dispc_regs *dispc, 
		unsigned long timeout_ticks)
{
	unsigned long dispc_control;

	dispc_control = dispc->control;
	if (dispc_control & DISPC_CONTROL_DIGITALENABLE)
		dispc_control |= DISPC_CONTROL_GODIGITAL;
	if (dispc_control & DISPC_CONTROL_LCDENABLE)
		dispc_control |= DISPC_CONTROL_GOLCD;
	dispc_reg_out(oinfo, DISPC_CONTROL, dispc_control);

	wait_for_go(oinfo, timeout_ticks);
	
	return;
}

/* Disable the display controller */
static void
omap24xxfb_disable(const struct omap24xxfb_info *oinfo, 
		unsigned long timeout_ticks)
{
	unsigned long timeout;

	if (dispc_reg_in(oinfo, DISPC_CONTROL) 
		& (DISPC_CONTROL_DIGITALENABLE | DISPC_CONTROL_LCDENABLE))
	{
		/* disable the display controller */
		dispc_reg_merge(oinfo, DISPC_CONTROL, 0, 
			DISPC_CONTROL_DIGITALENABLE | DISPC_CONTROL_LCDENABLE);
		/* wait for any frame in progress to complete */
		dispc_reg_out(oinfo, DISPC_IRQSTATUS, 
				DISPC_IRQSTATUS_FRAMEDONE);
		timeout = jiffies + timeout_ticks;
		while(!(dispc_reg_in(oinfo, DISPC_IRQSTATUS) 
				& DISPC_IRQSTATUS_FRAMEDONE)
			&& time_before(jiffies, timeout))
		{
			if (!in_atomic()) {
				set_current_state(TASK_INTERRUPTIBLE);
				schedule_timeout(1);
			} else
				udelay(100);
		}
	}

	return;
}

/* Reset the display controller */
static void
omap24xxfb_reset(const struct omap24xxfb_info *oinfo, 
		unsigned long timeout_ticks)
{
	unsigned long timeout;

	/* disable the display controller */
	omap24xxfb_disable(oinfo, timeout_ticks);
	
	/* reset the display controller */
	dispc_reg_out(oinfo, DISPC_SYSCONFIG, DISPC_SYSCONFIG_SOFTRESET);
	/* wait for reset to complete */
	timeout = jiffies + timeout_ticks;
	while (!(dispc_reg_in(oinfo, DISPC_SYSSTATUS) 
			& DISPC_SYSSTATUS_RESETDONE)
		&& time_before(jiffies, timeout))
	{
		if (!in_atomic()) {
			set_current_state(TASK_INTERRUPTIBLE);
			schedule_timeout(1);
		} else
			udelay(100);
	}
	if (!(dispc_reg_in(oinfo, DISPC_SYSSTATUS) & DISPC_SYSSTATUS_RESETDONE))
	{
		printk(KERN_WARNING FB_NAME 
			": timeout waiting for display controller reset\n");
	}
	/* remove the reset */
	dispc_reg_merge(oinfo, DISPC_SYSCONFIG, 0, DISPC_SYSCONFIG_SOFTRESET);

	return;
}

static void 
omap24xxfb_write_state(struct omap24xxfb_info *oinfo, 
		struct omap24xx_dispc_regs *dispc, unsigned long timeout_ticks)
{
	/* set the state of bits that are dynamically managed by the driver */
	dispc->sysconfig &= ~DISPC_SYSCONFIG_SOFTRESET;
	dispc->control &= ~(DISPC_CONTROL_GODIGITAL | DISPC_CONTROL_GOLCD);
	dispc->config |= (DISPC_CONFIG_LOADMODE_PGTABUSETB 
				| DISPC_CONFIG_LOADMODE_FRDATLEFR);

	/* enable vsync interrupts */
	dispc->irqenable = DISPC_IRQENABLE_EVSYNC_ODD 
		| DISPC_IRQENABLE_EVSYNC_EVEN | DISPC_IRQENABLE_VSYNC;

	/* This driver doesn't currently support the video windows, so 
	 * we force the palette/gamma table to be a palette table and 
	 * force both video windows to be disabled.
	 */
	dispc->config &= ~DISPC_CONFIG_PALETTEGAMMATABLE;

	/* disable the display controller */
	omap24xxfb_disable(oinfo, timeout_ticks);	

	/*
	 * Update the state of the display controller.
	 */
	
	dispc_reg_out(oinfo, DISPC_SYSCONFIG, dispc->sysconfig);
	dispc_reg_out(oinfo, DISPC_IRQENABLE, dispc->irqenable);
	dispc_reg_out(oinfo, DISPC_CONFIG, dispc->config);
	dispc_reg_out(oinfo, DISPC_DEFAULT_COLOR0, dispc->default_color0);
	dispc_reg_out(oinfo, DISPC_DEFAULT_COLOR1, dispc->default_color1);
	dispc_reg_out(oinfo, DISPC_TRANS_COLOR0, dispc->trans_color0);
	dispc_reg_out(oinfo, DISPC_TRANS_COLOR1, dispc->trans_color1);
	dispc_reg_out(oinfo, DISPC_LINE_NUMBER, dispc->line_number);
	dispc_reg_out(oinfo, DISPC_DATA_CYCLE1, dispc->data_cycle1);
	dispc_reg_out(oinfo, DISPC_DATA_CYCLE2, dispc->data_cycle2);
	dispc_reg_out(oinfo, DISPC_DATA_CYCLE3, dispc->data_cycle3);
	dispc_reg_out(oinfo, DISPC_TIMING_H, dispc->timing_h);
	dispc_reg_out(oinfo, DISPC_TIMING_V, dispc->timing_v);
	dispc_reg_out(oinfo, DISPC_POL_FREQ, dispc->pol_freq);
	dispc_reg_out(oinfo, DISPC_DIVISOR, dispc->divisor);
	dispc_reg_out(oinfo, DISPC_SIZE_LCD, dispc->size_lcd);
	dispc_reg_out(oinfo, DISPC_SIZE_DIG, dispc->size_dig);
	dispc_reg_out(oinfo, DISPC_GFX_BA0, dispc->gfx_ba0);
	dispc_reg_out(oinfo, DISPC_GFX_BA1, dispc->gfx_ba1);
	dispc_reg_out(oinfo, DISPC_GFX_POSITION, dispc->gfx_position);
	dispc_reg_out(oinfo, DISPC_GFX_SIZE, dispc->gfx_size);
	dispc_reg_out(oinfo, DISPC_GFX_ATTRIBUTES, dispc->gfx_attributes);
	dispc_reg_out(oinfo, DISPC_GFX_FIFO_THRESHOLD, 
			dispc->gfx_fifo_threshold);
	dispc_reg_out(oinfo, DISPC_GFX_ROW_INC, dispc->gfx_row_inc);
	dispc_reg_out(oinfo, DISPC_GFX_PIXEL_INC, dispc->gfx_pixel_inc);
	dispc_reg_out(oinfo, DISPC_GFX_WINDOW_SKIP, dispc->gfx_window_skip);
	dispc_reg_out(oinfo, DISPC_GFX_TABLE_BA, dispc->gfx_table_ba);
	dispc_reg_out(oinfo, DISPC_VID1_BA0, dispc->vid1_ba0);
	dispc_reg_out(oinfo, DISPC_VID1_BA1, dispc->vid1_ba1);
	dispc_reg_out(oinfo, DISPC_VID2_BA0, dispc->vid2_ba0);
	dispc_reg_out(oinfo, DISPC_VID2_BA1, dispc->vid2_ba1);
	dispc_reg_out(oinfo, DISPC_VID1_POSITION, dispc->vid1_position);
	dispc_reg_out(oinfo, DISPC_VID2_POSITION, dispc->vid2_position);
	dispc_reg_out(oinfo, DISPC_VID1_SIZE, dispc->vid1_size);
	dispc_reg_out(oinfo, DISPC_VID2_SIZE, dispc->vid2_size);
	dispc_reg_out(oinfo, DISPC_VID1_ATTRIBUTES, dispc->vid1_attributes);
	dispc_reg_out(oinfo, DISPC_VID2_ATTRIBUTES, dispc->vid2_attributes);
	dispc_reg_out(oinfo, DISPC_VID1_FIFO_THRESHOLD, 
			dispc->vid1_fifo_threshold);
	dispc_reg_out(oinfo, DISPC_VID2_FIFO_THRESHOLD, 
			dispc->vid2_fifo_threshold);
	dispc_reg_out(oinfo, DISPC_VID1_ROW_INC, dispc->vid1_row_inc);
	dispc_reg_out(oinfo, DISPC_VID2_ROW_INC, dispc->vid2_row_inc);
	dispc_reg_out(oinfo, DISPC_VID1_PIXEL_INC, dispc->vid1_pixel_inc);
	dispc_reg_out(oinfo, DISPC_VID2_PIXEL_INC, dispc->vid2_pixel_inc);
	dispc_reg_out(oinfo, DISPC_VID1_FIR, dispc->vid1_fir);
	dispc_reg_out(oinfo, DISPC_VID2_FIR, dispc->vid2_fir);
	dispc_reg_out(oinfo, DISPC_VID1_ACCU0, dispc->vid1_accu0);
	dispc_reg_out(oinfo, DISPC_VID1_ACCU1, dispc->vid1_accu1);
	dispc_reg_out(oinfo, DISPC_VID2_ACCU0, dispc->vid2_accu0);
	dispc_reg_out(oinfo, DISPC_VID2_ACCU1, dispc->vid2_accu1);
	dispc_reg_out(oinfo, DISPC_VID1_PICTURE_SIZE, 
			dispc->vid1_picture_size);
	dispc_reg_out(oinfo, DISPC_VID2_PICTURE_SIZE, 
			dispc->vid2_picture_size);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H0, dispc->vid1_fir_coef_h0);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H1, dispc->vid1_fir_coef_h1);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H2, dispc->vid1_fir_coef_h2);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H3, dispc->vid1_fir_coef_h3);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H4, dispc->vid1_fir_coef_h4);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H5, dispc->vid1_fir_coef_h5);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H6, dispc->vid1_fir_coef_h6);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_H7, dispc->vid1_fir_coef_h7);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H0, dispc->vid2_fir_coef_h0);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H1, dispc->vid2_fir_coef_h1);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H2, dispc->vid2_fir_coef_h2);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H3, dispc->vid2_fir_coef_h3);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H4, dispc->vid2_fir_coef_h4);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H5, dispc->vid2_fir_coef_h5);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H6, dispc->vid2_fir_coef_h6);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_H7, dispc->vid2_fir_coef_h7);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV0, dispc->vid1_fir_coef_hv0);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV1, dispc->vid1_fir_coef_hv1);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV2, dispc->vid1_fir_coef_hv2);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV3, dispc->vid1_fir_coef_hv3);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV4, dispc->vid1_fir_coef_hv4);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV5, dispc->vid1_fir_coef_hv5);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV6, dispc->vid1_fir_coef_hv6);
	dispc_reg_out(oinfo, DISPC_VID1_FIR_COEF_HV7, dispc->vid1_fir_coef_hv7);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV0, dispc->vid2_fir_coef_hv0);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV1, dispc->vid2_fir_coef_hv1);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV2, dispc->vid2_fir_coef_hv2);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV3, dispc->vid2_fir_coef_hv3);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV4, dispc->vid2_fir_coef_hv4);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV5, dispc->vid2_fir_coef_hv5);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV6, dispc->vid2_fir_coef_hv6);
	dispc_reg_out(oinfo, DISPC_VID2_FIR_COEF_HV7, dispc->vid2_fir_coef_hv7);
	dispc_reg_out(oinfo, DISPC_VID1_CONV_COEF0, dispc->vid1_conv_coef0);
	dispc_reg_out(oinfo, DISPC_VID2_CONV_COEF0, dispc->vid2_conv_coef0);
	dispc_reg_out(oinfo, DISPC_VID1_CONV_COEF1, dispc->vid1_conv_coef1);
	dispc_reg_out(oinfo, DISPC_VID2_CONV_COEF1, dispc->vid2_conv_coef1);
	dispc_reg_out(oinfo, DISPC_VID1_CONV_COEF2, dispc->vid1_conv_coef2);
	dispc_reg_out(oinfo, DISPC_VID2_CONV_COEF2, dispc->vid2_conv_coef2);
	dispc_reg_out(oinfo, DISPC_VID1_CONV_COEF3, dispc->vid1_conv_coef3);
	dispc_reg_out(oinfo, DISPC_VID2_CONV_COEF3, dispc->vid2_conv_coef3);
	dispc_reg_out(oinfo, DISPC_VID1_CONV_COEF4, dispc->vid1_conv_coef4);
	dispc_reg_out(oinfo, DISPC_VID2_CONV_COEF4, dispc->vid2_conv_coef4);

	/* enable the display controller */
	omap24xxfb_enable(oinfo, dispc, timeout_ticks);

	return;
}

static void 
omap24xxfb_save_state(struct omap24xxfb_info *oinfo, 
			struct omap24xx_dispc_regs *dispc)
{
	dispc->revision = dispc_reg_in(oinfo, DISPC_REVISION);
	dispc->sysconfig = dispc_reg_in(oinfo, DISPC_SYSCONFIG);
	dispc->sysstatus = dispc_reg_in(oinfo, DISPC_SYSSTATUS);
	dispc->irqstatus = dispc_reg_in(oinfo, DISPC_IRQSTATUS);
	dispc->irqenable = dispc_reg_in(oinfo, DISPC_IRQENABLE);
	dispc->control = dispc_reg_in(oinfo, DISPC_CONTROL);
	dispc->config = dispc_reg_in(oinfo, DISPC_CONFIG);
	dispc->capable = dispc_reg_in(oinfo, DISPC_CAPABLE);
	dispc->default_color0 = dispc_reg_in(oinfo, DISPC_DEFAULT_COLOR0);
	dispc->default_color1 = dispc_reg_in(oinfo, DISPC_DEFAULT_COLOR1);
	dispc->trans_color0 = dispc_reg_in(oinfo, DISPC_TRANS_COLOR0);
	dispc->trans_color1 = dispc_reg_in(oinfo, DISPC_TRANS_COLOR1);
	dispc->line_status = dispc_reg_in(oinfo, DISPC_LINE_STATUS);
	dispc->line_number = dispc_reg_in(oinfo, DISPC_LINE_NUMBER);
	dispc->data_cycle1 = dispc_reg_in(oinfo, DISPC_DATA_CYCLE1);
	dispc->data_cycle2 = dispc_reg_in(oinfo, DISPC_DATA_CYCLE2);
	dispc->data_cycle3 = dispc_reg_in(oinfo, DISPC_DATA_CYCLE3);
	dispc->timing_h = dispc_reg_in(oinfo, DISPC_TIMING_H);
	dispc->timing_v = dispc_reg_in(oinfo, DISPC_TIMING_V);
	dispc->pol_freq = dispc_reg_in(oinfo, DISPC_POL_FREQ);
	dispc->divisor = dispc_reg_in(oinfo, DISPC_DIVISOR);
	dispc->size_lcd = dispc_reg_in(oinfo, DISPC_SIZE_LCD);
	dispc->size_dig = dispc_reg_in(oinfo, DISPC_SIZE_DIG);
	dispc->gfx_ba0 = dispc_reg_in(oinfo, DISPC_GFX_BA0);
	dispc->gfx_ba1 = dispc_reg_in(oinfo, DISPC_GFX_BA1);
	dispc->gfx_position = dispc_reg_in(oinfo, DISPC_GFX_POSITION);
	dispc->gfx_size = dispc_reg_in(oinfo, DISPC_GFX_SIZE);
	dispc->gfx_attributes = dispc_reg_in(oinfo, DISPC_GFX_ATTRIBUTES);
	dispc->gfx_fifo_size = dispc_reg_in(oinfo, DISPC_GFX_FIFO_SIZE);
	dispc->gfx_fifo_threshold = 
		dispc_reg_in(oinfo, DISPC_GFX_FIFO_THRESHOLD);
	dispc->gfx_row_inc = dispc_reg_in(oinfo, DISPC_GFX_ROW_INC);
	dispc->gfx_pixel_inc = dispc_reg_in(oinfo, DISPC_GFX_PIXEL_INC);
	dispc->gfx_window_skip = dispc_reg_in(oinfo, DISPC_GFX_WINDOW_SKIP);
	dispc->gfx_table_ba = dispc_reg_in(oinfo, DISPC_GFX_TABLE_BA);
	dispc->vid1_ba0 = dispc_reg_in(oinfo, DISPC_VID1_BA0);
	dispc->vid1_ba1 = dispc_reg_in(oinfo, DISPC_VID1_BA1);
	dispc->vid2_ba0 = dispc_reg_in(oinfo, DISPC_VID2_BA0);
	dispc->vid2_ba1 = dispc_reg_in(oinfo, DISPC_VID2_BA1);
	dispc->vid1_position = dispc_reg_in(oinfo, DISPC_VID1_POSITION);
	dispc->vid2_position = dispc_reg_in(oinfo, DISPC_VID2_POSITION);
	dispc->vid1_size = dispc_reg_in(oinfo, DISPC_VID1_SIZE);
	dispc->vid2_size = dispc_reg_in(oinfo, DISPC_VID2_SIZE);
	dispc->vid1_attributes = dispc_reg_in(oinfo, DISPC_VID1_ATTRIBUTES);
	dispc->vid2_attributes = dispc_reg_in(oinfo, DISPC_VID2_ATTRIBUTES);
	dispc->vid1_fifo_size = dispc_reg_in(oinfo, DISPC_VID1_FIFO_SIZE);
	dispc->vid2_fifo_size = dispc_reg_in(oinfo, DISPC_VID2_FIFO_SIZE);
	dispc->vid1_fifo_threshold = 
		dispc_reg_in(oinfo, DISPC_VID1_FIFO_THRESHOLD);
	dispc->vid2_fifo_threshold = 
		dispc_reg_in(oinfo, DISPC_VID2_FIFO_THRESHOLD);
	dispc->vid1_row_inc = dispc_reg_in(oinfo, DISPC_VID1_ROW_INC);
	dispc->vid2_row_inc = dispc_reg_in(oinfo, DISPC_VID2_ROW_INC);
	dispc->vid1_pixel_inc = dispc_reg_in(oinfo, DISPC_VID1_PIXEL_INC);
	dispc->vid2_pixel_inc = dispc_reg_in(oinfo, DISPC_VID2_PIXEL_INC);
	dispc->vid1_fir = dispc_reg_in(oinfo, DISPC_VID1_FIR);
	dispc->vid2_fir = dispc_reg_in(oinfo, DISPC_VID2_FIR);
	dispc->vid1_accu0 = dispc_reg_in(oinfo, DISPC_VID1_ACCU0);
	dispc->vid1_accu1 = dispc_reg_in(oinfo, DISPC_VID1_ACCU1);
	dispc->vid2_accu0 = dispc_reg_in(oinfo, DISPC_VID2_ACCU0);
	dispc->vid2_accu1 = dispc_reg_in(oinfo, DISPC_VID2_ACCU1);
	dispc->vid1_picture_size = dispc_reg_in(oinfo, DISPC_VID1_PICTURE_SIZE);
	dispc->vid2_picture_size = dispc_reg_in(oinfo, DISPC_VID2_PICTURE_SIZE);
	dispc->vid1_fir_coef_h0 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H0);
	dispc->vid1_fir_coef_h1 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H1);
	dispc->vid1_fir_coef_h2 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H2);
	dispc->vid1_fir_coef_h3 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H3);
	dispc->vid1_fir_coef_h4 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H4);
	dispc->vid1_fir_coef_h5 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H5);
	dispc->vid1_fir_coef_h6 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H6);
	dispc->vid1_fir_coef_h7 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_H7);
	dispc->vid2_fir_coef_h0 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H0);
	dispc->vid2_fir_coef_h1 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H1);
	dispc->vid2_fir_coef_h2 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H2);
	dispc->vid2_fir_coef_h3 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H3);
	dispc->vid2_fir_coef_h4 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H4);
	dispc->vid2_fir_coef_h5 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H5);
	dispc->vid2_fir_coef_h6 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H6);
	dispc->vid2_fir_coef_h7 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_H7);
	dispc->vid1_fir_coef_hv0 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV0);
	dispc->vid1_fir_coef_hv1 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV1);
	dispc->vid1_fir_coef_hv2 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV2);
	dispc->vid1_fir_coef_hv3 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV3);
	dispc->vid1_fir_coef_hv4 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV4);
	dispc->vid1_fir_coef_hv5 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV5);
	dispc->vid1_fir_coef_hv6 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV6);
	dispc->vid1_fir_coef_hv7 = dispc_reg_in(oinfo, DISPC_VID1_FIR_COEF_HV7);
	dispc->vid2_fir_coef_hv0 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV0);
	dispc->vid2_fir_coef_hv1 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV1);
	dispc->vid2_fir_coef_hv2 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV2);
	dispc->vid2_fir_coef_hv3 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV3);
	dispc->vid2_fir_coef_hv4 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV4);
	dispc->vid2_fir_coef_hv5 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV5);
	dispc->vid2_fir_coef_hv6 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV6);
	dispc->vid2_fir_coef_hv7 = dispc_reg_in(oinfo, DISPC_VID2_FIR_COEF_HV7);
	dispc->vid1_conv_coef0 = dispc_reg_in(oinfo, DISPC_VID1_CONV_COEF0);
	dispc->vid2_conv_coef0 = dispc_reg_in(oinfo, DISPC_VID2_CONV_COEF0);
	dispc->vid1_conv_coef1 = dispc_reg_in(oinfo, DISPC_VID1_CONV_COEF1);
	dispc->vid2_conv_coef1 = dispc_reg_in(oinfo, DISPC_VID2_CONV_COEF1);
	dispc->vid1_conv_coef2 = dispc_reg_in(oinfo, DISPC_VID1_CONV_COEF2);
	dispc->vid2_conv_coef2 = dispc_reg_in(oinfo, DISPC_VID2_CONV_COEF2);
	dispc->vid1_conv_coef3 = dispc_reg_in(oinfo, DISPC_VID1_CONV_COEF3);
	dispc->vid2_conv_coef3 = dispc_reg_in(oinfo, DISPC_VID2_CONV_COEF3);
	dispc->vid1_conv_coef4 = dispc_reg_in(oinfo, DISPC_VID1_CONV_COEF4);
	dispc->vid2_conv_coef4 = dispc_reg_in(oinfo, DISPC_VID2_CONV_COEF4);

	return;
}

/* Wait for a vsync interrupt.  This routine sleeps so it can only be called 
 * from process context.
 */
static int
omap24xxfb_wait_for_vsync(struct omap24xxfb_info *oinfo)
{
	wait_queue_t wq;
	unsigned long cnt;
	int ret;

	init_waitqueue_entry(&wq, current);

	cnt = oinfo->vsync_cnt;
	ret = wait_event_interruptible_timeout(oinfo->vsync_wait, 
		cnt != oinfo->vsync_cnt, oinfo->timeout);
	if (ret < 0)
		return ret;
	if (ret == 0)
		return -ETIMEDOUT;

	return 0;
}

/* Interrupt service routine. */
static irqreturn_t
omap24xxfb_isr(int irq, void *arg, struct pt_regs *regs)
{
	struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) arg;
	unsigned long dispc_irqstatus;

	dispc_irqstatus = dispc_reg_in(oinfo, DISPC_IRQSTATUS);

	/* ack the interrupt */
	dispc_reg_out(oinfo, DISPC_IRQSTATUS, dispc_irqstatus);

	if (dispc_irqstatus & 
		(DISPC_IRQSTATUS_EVSYNC_ODD | DISPC_IRQSTATUS_EVSYNC_EVEN 
		| DISPC_IRQSTATUS_VSYNC))
	{
		++oinfo->vsync_cnt;
		wake_up_interruptible(&oinfo->vsync_wait);
	}
	return IRQ_HANDLED;
}


	/*
	 * fbops functions
	 */

/*
 *	omap24xxfb_check_var - Validates a var passed in. 
 *	@var: frame buffer variable screen structure
 *	@info: frame buffer structure that represents a single frame buffer 
 *
 *	Returns negative errno on error, or zero on success.  The var info on 
 *	exit may be different than the var info on entry.
 *
 *	This function accepts any bits-per-pixel value in the range 0 to 32 
 *	(0 to 8 for monochrome displays).  If the specified number of 
 *	bits-per-pixel isn't supported, then the next greater number of 
 *	bits-per-pixel will be substituted.  This function differentiates 
 *	between color depths of 12 and 16 (which both have 16 bits-per-pixel) 
 *	by checking to see if the sum of the lengths of the RGB fields is 12, 
 *	in which case the color depth is assumed to be 12.  Except for 
 *	differentiating between 12-bit and 16-bit color depths, the values 
 *	passed in var->red, var->green, and var->blue are ignored and replaced 
 *	with the correct values for the specified color depth.
 *
 *	The xres/yres variables in the var screeninfo specify the size of the 
 *	graphics window.  The graphics window size must not be larger than the 
 *	physical display size nor larger than the size of the framebuffer.
 *	The xres_virtual/yres_virtual values in the var screeninfo specify the 
 *	size of the framebuffer in memory.   The framebuffer must not be smaller
 *	than the size of the graphics window.  The display_xres/display_yres 
 *	values in the private info structure specify the size of the display.  
 *	The display must not be smaller than the graphics window.  The display 
 *	size is a compile-time (or perhaps initialization time) configuration 
 *	option and cannot be changed by the user.  The xoffset/yoffset variables 
 *	in the var screeninfo specify the offset of the graphics window within 
 *	the framebuffer.  There is no means for the user to specify the offset 
 *	of the graphics window on the display, so that offset will always be 
 *	zero unless the board-specific mode changing function implements some 
 *	other behavior, such as centering.
 */
static int
omap24xxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
	const struct omap24xxfb_info *oinfo = 
				(const struct omap24xxfb_info *) info->par;