tg3.h

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/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
 *
 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller ([e-mail])
 * Copyright (C) 2001 Jeff Garzik ([e-mail])
 * Copyright (C) 2004 Sun Microsystems Inc.
 */

#ifndef _T3_H
#define _T3_H

#define TG3_64BIT_REG_HIGH		0x00UL
#define TG3_64BIT_REG_LOW		0x04UL

/* Descriptor block info. */
#define TG3_BDINFO_HOST_ADDR		0x0UL /* 64-bit */
#define TG3_BDINFO_MAXLEN_FLAGS		0x8UL /* 32-bit */
#define  BDINFO_FLAGS_USE_EXT_RECV	 0x00000001 /* ext rx_buffer_desc */
#define  BDINFO_FLAGS_DISABLED		 0x00000002
#define  BDINFO_FLAGS_MAXLEN_MASK	 0xffff0000
#define  BDINFO_FLAGS_MAXLEN_SHIFT	 16
#define TG3_BDINFO_NIC_ADDR		0xcUL /* 32-bit */
#define TG3_BDINFO_SIZE			0x10UL

#define RX_COPY_THRESHOLD  		256

#define RX_STD_MAX_SIZE			1536
#define RX_STD_MAX_SIZE_5705		512
#define RX_JUMBO_MAX_SIZE		0xdeadbeef /* XXX */

/* First 256 bytes are a mirror of PCI config space. */
#define TG3PCI_VENDOR			0x00000000
#define  TG3PCI_VENDOR_BROADCOM		 0x14e4
#define TG3PCI_DEVICE			0x00000002
#define  TG3PCI_DEVICE_TIGON3_1		 0x1644 /* BCM5700 */
#define  TG3PCI_DEVICE_TIGON3_2		 0x1645 /* BCM5701 */
#define  TG3PCI_DEVICE_TIGON3_3		 0x1646 /* BCM5702 */
#define  TG3PCI_DEVICE_TIGON3_4		 0x1647 /* BCM5703 */
#define TG3PCI_COMMAND			0x00000004
#define TG3PCI_STATUS			0x00000006
#define TG3PCI_CCREVID			0x00000008
#define TG3PCI_CACHELINESZ		0x0000000c
#define TG3PCI_LATTIMER			0x0000000d
#define TG3PCI_HEADERTYPE		0x0000000e
#define TG3PCI_BIST			0x0000000f
#define TG3PCI_BASE0_LOW		0x00000010
#define TG3PCI_BASE0_HIGH		0x00000014
/* 0x18 --> 0x2c unused */
#define TG3PCI_SUBSYSVENID		0x0000002c
#define TG3PCI_SUBSYSID			0x0000002e
#define TG3PCI_ROMADDR			0x00000030
#define TG3PCI_CAPLIST			0x00000034
/* 0x35 --> 0x3c unused */
#define TG3PCI_IRQ_LINE			0x0000003c
#define TG3PCI_IRQ_PIN			0x0000003d
#define TG3PCI_MIN_GNT			0x0000003e
#define TG3PCI_MAX_LAT			0x0000003f
#define TG3PCI_X_CAPS			0x00000040
#define  PCIX_CAPS_RELAXED_ORDERING	 0x00020000
#define  PCIX_CAPS_SPLIT_MASK		 0x00700000
#define  PCIX_CAPS_SPLIT_SHIFT		 20
#define  PCIX_CAPS_BURST_MASK		 0x000c0000
#define  PCIX_CAPS_BURST_SHIFT		 18
#define  PCIX_CAPS_MAX_BURST_CPIOB	 2
#define TG3PCI_PM_CAP_PTR		0x00000041
#define TG3PCI_X_COMMAND		0x00000042
#define TG3PCI_X_STATUS			0x00000044
#define TG3PCI_PM_CAP_ID		0x00000048
#define TG3PCI_VPD_CAP_PTR		0x00000049
#define TG3PCI_PM_CAPS			0x0000004a
#define TG3PCI_PM_CTRL_STAT		0x0000004c
#define TG3PCI_BR_SUPP_EXT		0x0000004e
#define TG3PCI_PM_DATA			0x0000004f
#define TG3PCI_VPD_CAP_ID		0x00000050
#define TG3PCI_MSI_CAP_PTR		0x00000051
#define TG3PCI_VPD_ADDR_FLAG		0x00000052
#define  VPD_ADDR_FLAG_WRITE		0x00008000
#define TG3PCI_VPD_DATA			0x00000054
#define TG3PCI_MSI_CAP_ID		0x00000058
#define TG3PCI_NXT_CAP_PTR		0x00000059
#define TG3PCI_MSI_CTRL			0x0000005a
#define TG3PCI_MSI_ADDR_LOW		0x0000005c
#define TG3PCI_MSI_ADDR_HIGH		0x00000060
#define TG3PCI_MSI_DATA			0x00000064
/* 0x66 --> 0x68 unused */
#define TG3PCI_MISC_HOST_CTRL		0x00000068
#define  MISC_HOST_CTRL_CLEAR_INT	 0x00000001
#define  MISC_HOST_CTRL_MASK_PCI_INT	 0x00000002
#define  MISC_HOST_CTRL_BYTE_SWAP	 0x00000004
#define  MISC_HOST_CTRL_WORD_SWAP	 0x00000008
#define  MISC_HOST_CTRL_PCISTATE_RW	 0x00000010
#define  MISC_HOST_CTRL_CLKREG_RW	 0x00000020
#define  MISC_HOST_CTRL_REGWORD_SWAP	 0x00000040
#define  MISC_HOST_CTRL_INDIR_ACCESS	 0x00000080
#define  MISC_HOST_CTRL_IRQ_MASK_MODE	 0x00000100
#define  MISC_HOST_CTRL_TAGGED_STATUS	 0x00000200
#define  MISC_HOST_CTRL_CHIPREV		 0xffff0000
#define  MISC_HOST_CTRL_CHIPREV_SHIFT	 16
#define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
	 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
	  MISC_HOST_CTRL_CHIPREV_SHIFT)
#define  CHIPREV_ID_5700_A0		 0x7000
#define  CHIPREV_ID_5700_A1		 0x7001
#define  CHIPREV_ID_5700_B0		 0x7100
#define  CHIPREV_ID_5700_B1		 0x7101
#define  CHIPREV_ID_5700_B3		 0x7102
#define  CHIPREV_ID_5700_ALTIMA		 0x7104
#define  CHIPREV_ID_5700_C0		 0x7200
#define  CHIPREV_ID_5701_A0		 0x0000
#define  CHIPREV_ID_5701_B0		 0x0100
#define  CHIPREV_ID_5701_B2		 0x0102
#define  CHIPREV_ID_5701_B5		 0x0105
#define  CHIPREV_ID_5703_A0		 0x1000
#define  CHIPREV_ID_5703_A1		 0x1001
#define  CHIPREV_ID_5703_A2		 0x1002
#define  CHIPREV_ID_5703_A3		 0x1003
#define  CHIPREV_ID_5704_A0		 0x2000
#define  CHIPREV_ID_5704_A1		 0x2001
#define  CHIPREV_ID_5704_A2		 0x2002
#define  CHIPREV_ID_5704_A3		 0x2003
#define  CHIPREV_ID_5705_A0		 0x3000
#define  CHIPREV_ID_5705_A1		 0x3001
#define  CHIPREV_ID_5705_A2		 0x3002
#define  CHIPREV_ID_5705_A3		 0x3003
#define  CHIPREV_ID_5750_A0		 0x4000
#define  CHIPREV_ID_5750_A1		 0x4001
#define  CHIPREV_ID_5750_A3		 0x4003
#define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
#define   ASIC_REV_5700			 0x07
#define   ASIC_REV_5701			 0x00
#define   ASIC_REV_5703			 0x01
#define   ASIC_REV_5704			 0x02
#define   ASIC_REV_5705			 0x03
#define   ASIC_REV_5750			 0x04
#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
#define   CHIPREV_5700_AX		 0x70
#define   CHIPREV_5700_BX		 0x71
#define   CHIPREV_5700_CX		 0x72
#define   CHIPREV_5701_AX		 0x00
#define   CHIPREV_5703_AX		 0x10
#define   CHIPREV_5704_AX		 0x20
#define   CHIPREV_5704_BX		 0x21
#define  GET_METAL_REV(CHIP_REV_ID)	((CHIP_REV_ID) & 0xff)
#define   METAL_REV_A0			 0x00
#define   METAL_REV_A1			 0x01
#define   METAL_REV_B0			 0x00
#define   METAL_REV_B1			 0x01
#define   METAL_REV_B2			 0x02
#define TG3PCI_DMA_RW_CTRL		0x0000006c
#define  DMA_RWCTRL_MIN_DMA		 0x000000ff
#define  DMA_RWCTRL_MIN_DMA_SHIFT	 0
#define  DMA_RWCTRL_READ_BNDRY_MASK	 0x00000700
#define  DMA_RWCTRL_READ_BNDRY_DISAB	 0x00000000
#define  DMA_RWCTRL_READ_BNDRY_16	 0x00000100
#define  DMA_RWCTRL_READ_BNDRY_128_PCIX	 0x00000100
#define  DMA_RWCTRL_READ_BNDRY_32	 0x00000200
#define  DMA_RWCTRL_READ_BNDRY_256_PCIX	 0x00000200
#define  DMA_RWCTRL_READ_BNDRY_64	 0x00000300
#define  DMA_RWCTRL_READ_BNDRY_384_PCIX	 0x00000300
#define  DMA_RWCTRL_READ_BNDRY_128	 0x00000400
#define  DMA_RWCTRL_READ_BNDRY_256	 0x00000500
#define  DMA_RWCTRL_READ_BNDRY_512	 0x00000600
#define  DMA_RWCTRL_READ_BNDRY_1024	 0x00000700
#define  DMA_RWCTRL_WRITE_BNDRY_MASK	 0x00003800
#define  DMA_RWCTRL_WRITE_BNDRY_DISAB	 0x00000000
#define  DMA_RWCTRL_WRITE_BNDRY_16	 0x00000800
#define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
#define  DMA_RWCTRL_WRITE_BNDRY_32	 0x00001000
#define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
#define  DMA_RWCTRL_WRITE_BNDRY_64	 0x00001800
#define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
#define  DMA_RWCTRL_WRITE_BNDRY_128	 0x00002000
#define  DMA_RWCTRL_WRITE_BNDRY_256	 0x00002800
#define  DMA_RWCTRL_WRITE_BNDRY_512	 0x00003000
#define  DMA_RWCTRL_WRITE_BNDRY_1024	 0x00003800
#define  DMA_RWCTRL_ONE_DMA		 0x00004000
#define  DMA_RWCTRL_READ_WATER		 0x00070000
#define  DMA_RWCTRL_READ_WATER_SHIFT	 16
#define  DMA_RWCTRL_WRITE_WATER		 0x00380000
#define  DMA_RWCTRL_WRITE_WATER_SHIFT	 19
#define  DMA_RWCTRL_USE_MEM_READ_MULT	 0x00400000
#define  DMA_RWCTRL_ASSERT_ALL_BE	 0x00800000
#define  DMA_RWCTRL_PCI_READ_CMD	 0x0f000000
#define  DMA_RWCTRL_PCI_READ_CMD_SHIFT	 24
#define  DMA_RWCTRL_PCI_WRITE_CMD	 0xf0000000
#define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT	 28
#define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE	 0x10000000
#define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
#define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
#define TG3PCI_PCISTATE			0x00000070
#define  PCISTATE_FORCE_RESET		 0x00000001
#define  PCISTATE_INT_NOT_ACTIVE	 0x00000002
#define  PCISTATE_CONV_PCI_MODE		 0x00000004
#define  PCISTATE_BUS_SPEED_HIGH	 0x00000008
#define  PCISTATE_BUS_32BIT		 0x00000010
#define  PCISTATE_ROM_ENABLE		 0x00000020
#define  PCISTATE_ROM_RETRY_ENABLE	 0x00000040
#define  PCISTATE_FLAT_VIEW		 0x00000100
#define  PCISTATE_RETRY_SAME_DMA	 0x00002000
#define TG3PCI_CLOCK_CTRL		0x00000074
#define  CLOCK_CTRL_CORECLK_DISABLE	 0x00000200
#define  CLOCK_CTRL_RXCLK_DISABLE	 0x00000400
#define  CLOCK_CTRL_TXCLK_DISABLE	 0x00000800
#define  CLOCK_CTRL_ALTCLK		 0x00001000
#define  CLOCK_CTRL_PWRDOWN_PLL133	 0x00008000
#define  CLOCK_CTRL_44MHZ_CORE		 0x00040000
#define  CLOCK_CTRL_625_CORE		 0x00100000
#define  CLOCK_CTRL_FORCE_CLKRUN	 0x00200000
#define  CLOCK_CTRL_CLKRUN_OENABLE	 0x00400000
#define  CLOCK_CTRL_DELAY_PCI_GRANT	 0x80000000
#define TG3PCI_REG_BASE_ADDR		0x00000078
#define TG3PCI_MEM_WIN_BASE_ADDR	0x0000007c
#define TG3PCI_REG_DATA			0x00000080
#define TG3PCI_MEM_WIN_DATA		0x00000084
#define TG3PCI_MODE_CTRL		0x00000088
#define TG3PCI_MISC_CFG			0x0000008c
#define TG3PCI_MISC_LOCAL_CTRL		0x00000090
/* 0x94 --> 0x98 unused */
#define TG3PCI_STD_RING_PROD_IDX	0x00000098 /* 64-bit */
#define TG3PCI_RCV_RET_RING_CON_IDX	0x000000a0 /* 64-bit */
#define TG3PCI_SND_PROD_IDX		0x000000a8 /* 64-bit */
/* 0xb0 --> 0xb8 unused */
#define TG3PCI_DUAL_MAC_CTRL		0x000000b8
#define  DUAL_MAC_CTRL_CH_MASK		 0x00000003
#define  DUAL_MAC_CTRL_ID		 0x00000004
/* 0xbc --> 0x100 unused */

/* 0x100 --> 0x200 unused */

/* Mailbox registers */
#define MAILBOX_INTERRUPT_0		0x00000200 /* 64-bit */
#define MAILBOX_INTERRUPT_1		0x00000208 /* 64-bit */
#define MAILBOX_INTERRUPT_2		0x00000210 /* 64-bit */
#define MAILBOX_INTERRUPT_3		0x00000218 /* 64-bit */
#define MAILBOX_GENERAL_0		0x00000220 /* 64-bit */
#define MAILBOX_GENERAL_1		0x00000228 /* 64-bit */
#define MAILBOX_GENERAL_2		0x00000230 /* 64-bit */
#define MAILBOX_GENERAL_3		0x00000238 /* 64-bit */
#define MAILBOX_GENERAL_4		0x00000240 /* 64-bit */
#define MAILBOX_GENERAL_5		0x00000248 /* 64-bit */
#define MAILBOX_GENERAL_6		0x00000250 /* 64-bit */
#define MAILBOX_GENERAL_7		0x00000258 /* 64-bit */
#define MAILBOX_RELOAD_STAT		0x00000260 /* 64-bit */
#define MAILBOX_RCV_STD_PROD_IDX	0x00000268 /* 64-bit */
#define MAILBOX_RCV_JUMBO_PROD_IDX	0x00000270 /* 64-bit */
#define MAILBOX_RCV_MINI_PROD_IDX	0x00000278 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_0	0x00000280 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_1	0x00000288 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_2	0x00000290 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_3	0x00000298 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_4	0x000002a0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_5	0x000002a8 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_6	0x000002b0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_7	0x000002b8 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_8	0x000002c0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_9	0x000002c8 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_10	0x000002d0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_11	0x000002d8 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_12	0x000002e0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_13	0x000002e8 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_14	0x000002f0 /* 64-bit */
#define MAILBOX_RCVRET_CON_IDX_15	0x000002f8 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_0	0x00000300 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_1	0x00000308 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_2	0x00000310 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_3	0x00000318 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_4	0x00000320 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_5	0x00000328 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_6	0x00000330 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_7	0x00000338 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_8	0x00000340 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_9	0x00000348 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_10	0x00000350 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_11	0x00000358 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_12	0x00000360 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_13	0x00000368 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_14	0x00000370 /* 64-bit */
#define MAILBOX_SNDHOST_PROD_IDX_15	0x00000378 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_0	0x00000380 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_1	0x00000388 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_2	0x00000390 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_3	0x00000398 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_4	0x000003a0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_5	0x000003a8 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_6	0x000003b0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_7	0x000003b8 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_8	0x000003c0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_9	0x000003c8 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_10	0x000003d0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_11	0x000003d8 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_12	0x000003e0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_13	0x000003e8 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_14	0x000003f0 /* 64-bit */
#define MAILBOX_SNDNIC_PROD_IDX_15	0x000003f8 /* 64-bit */

/* MAC control registers */
#define MAC_MODE			0x00000400
#define  MAC_MODE_RESET			 0x00000001
#define  MAC_MODE_HALF_DUPLEX		 0x00000002
#define  MAC_MODE_PORT_MODE_MASK	 0x0000000c
#define  MAC_MODE_PORT_MODE_TBI		 0x0000000c
#define  MAC_MODE_PORT_MODE_GMII	 0x00000008
#define  MAC_MODE_PORT_MODE_MII		 0x00000004
#define  MAC_MODE_PORT_MODE_NONE	 0x00000000
#define  MAC_MODE_PORT_INT_LPBACK	 0x00000010
#define  MAC_MODE_TAGGED_MAC_CTRL	 0x00000080
#define  MAC_MODE_TX_BURSTING		 0x00000100
#define  MAC_MODE_MAX_DEFER		 0x00000200
#define  MAC_MODE_LINK_POLARITY		 0x00000400
#define  MAC_MODE_RXSTAT_ENABLE		 0x00000800
#define  MAC_MODE_RXSTAT_CLEAR		 0x00001000
#define  MAC_MODE_RXSTAT_FLUSH		 0x00002000
#define  MAC_MODE_TXSTAT_ENABLE		 0x00004000
#define  MAC_MODE_TXSTAT_CLEAR		 0x00008000
#define  MAC_MODE_TXSTAT_FLUSH		 0x00010000
#define  MAC_MODE_SEND_CONFIGS		 0x00020000
#define  MAC_MODE_MAGIC_PKT_ENABLE	 0x00040000
#define  MAC_MODE_ACPI_ENABLE		 0x00080000
#define  MAC_MODE_MIP_ENABLE		 0x00100000
#define  MAC_MODE_TDE_ENABLE		 0x00200000
#define  MAC_MODE_RDE_ENABLE		 0x00400000