via-velocity.h

Linux Kernel 2.6.9 for OMAP1710

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software may be redistributed and/or modified under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 *
 * File: via-velocity.h
 *
 * Purpose: Header file to define driver's private structures.
 *
 * Author: Chuang Liang-Shing, AJ Jiang
 *
 * Date: Jan 24, 2003
 */


#ifndef VELOCITY_H
#define VELOCITY_H

#define VELOCITY_TX_CSUM_SUPPORT

#define VELOCITY_NAME          "via-velocity"
#define VELOCITY_FULL_DRV_NAM  "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
#define VELOCITY_VERSION       "1.13"

#define PKT_BUF_SZ          1540

#define MAX_UNITS           8
#define OPTION_DEFAULT      { [0 ... MAX_UNITS-1] = -1}

#define REV_ID_VT6110       (0)

#define BYTE_REG_BITS_ON(x,p)       do { writeb(readb((p))|(x),(p));} while (0)
#define WORD_REG_BITS_ON(x,p)       do { writew(readw((p))|(x),(p));} while (0)
#define DWORD_REG_BITS_ON(x,p)      do { writel(readl((p))|(x),(p));} while (0)

#define BYTE_REG_BITS_IS_ON(x,p)    (readb((p)) & (x))
#define WORD_REG_BITS_IS_ON(x,p)    (readw((p)) & (x))
#define DWORD_REG_BITS_IS_ON(x,p)   (readl((p)) & (x))

#define BYTE_REG_BITS_OFF(x,p)      do { writeb(readb((p)) & (~(x)),(p));} while (0)
#define WORD_REG_BITS_OFF(x,p)      do { writew(readw((p)) & (~(x)),(p));} while (0)
#define DWORD_REG_BITS_OFF(x,p)     do { writel(readl((p)) & (~(x)),(p));} while (0)

#define BYTE_REG_BITS_SET(x,m,p)    do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
#define WORD_REG_BITS_SET(x,m,p)    do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
#define DWORD_REG_BITS_SET(x,m,p)   do { writel( (readl((p)) & (~(m)))|(x),(p));}  while (0)

#define VAR_USED(p)     do {(p)=(p);} while (0)

/*
 * Purpose: Structures for MAX RX/TX descriptors.
 */


#define B_OWNED_BY_CHIP     1
#define B_OWNED_BY_HOST     0

/*
 * Bits in the RSR0 register
 */

#define RSR_DETAG          0x0080
#define RSR_SNTAG          0x0040
#define RSR_RXER           0x0020
#define RSR_RL             0x0010
#define RSR_CE             0x0008
#define RSR_FAE            0x0004
#define RSR_CRC            0x0002
#define RSR_VIDM           0x0001

/*
 * Bits in the RSR1 register
 */

#define RSR_RXOK           0x8000	// rx OK
#define RSR_PFT            0x4000	// Perfect filtering address match
#define RSR_MAR            0x2000	// MAC accept multicast address packet
#define RSR_BAR            0x1000	// MAC accept broadcast address packet
#define RSR_PHY            0x0800	// MAC accept physical address packet
#define RSR_VTAG           0x0400	// 802.1p/1q tagging packet indicator
#define RSR_STP            0x0200	// start of packet
#define RSR_EDP            0x0100	// end of packet

/*
 * Bits in the RSR1 register
 */

#define RSR1_RXOK           0x80	// rx OK
#define RSR1_PFT            0x40	// Perfect filtering address match
#define RSR1_MAR            0x20	// MAC accept multicast address packet
#define RSR1_BAR            0x10	// MAC accept broadcast address packet
#define RSR1_PHY            0x08	// MAC accept physical address packet
#define RSR1_VTAG           0x04	// 802.1p/1q tagging packet indicator
#define RSR1_STP            0x02	// start of packet
#define RSR1_EDP            0x01	// end of packet

/*
 * Bits in the CSM register
 */

#define CSM_IPOK            0x40	//IP Checkusm validatiaon ok
#define CSM_TUPOK           0x20	//TCP/UDP Checkusm validatiaon ok
#define CSM_FRAG            0x10	//Fragment IP datagram
#define CSM_IPKT            0x04	//Received an IP packet
#define CSM_TCPKT           0x02	//Received a TCP packet
#define CSM_UDPKT           0x01	//Received a UDP packet

/*
 * Bits in the TSR0 register
 */

#define TSR0_ABT            0x0080	// Tx abort because of excessive collision
#define TSR0_OWT            0x0040	// Jumbo frame Tx abort
#define TSR0_OWC            0x0020	// Out of window collision
#define TSR0_COLS           0x0010	// experience collision in this transmit event
#define TSR0_NCR3           0x0008	// collision retry counter[3]
#define TSR0_NCR2           0x0004	// collision retry counter[2]
#define TSR0_NCR1           0x0002	// collision retry counter[1]
#define TSR0_NCR0           0x0001	// collision retry counter[0]
#define TSR0_TERR           0x8000	//
#define TSR0_FDX            0x4000	// current transaction is serviced by full duplex mode
#define TSR0_GMII           0x2000	// current transaction is serviced by GMII mode
#define TSR0_LNKFL          0x1000	// packet serviced during link down
#define TSR0_SHDN           0x0400	// shutdown case
#define TSR0_CRS            0x0200	// carrier sense lost
#define TSR0_CDH            0x0100	// AQE test fail (CD heartbeat)

/*
 * Bits in the TSR1 register
 */

#define TSR1_TERR           0x80	//
#define TSR1_FDX            0x40	// current transaction is serviced by full duplex mode
#define TSR1_GMII           0x20	// current transaction is serviced by GMII mode
#define TSR1_LNKFL          0x10	// packet serviced during link down
#define TSR1_SHDN           0x04	// shutdown case
#define TSR1_CRS            0x02	// carrier sense lost
#define TSR1_CDH            0x01	// AQE test fail (CD heartbeat)

//
// Bits in the TCR0 register
//
#define TCR0_TIC            0x80	// assert interrupt immediately while descriptor has been send complete
#define TCR0_PIC            0x40	// priority interrupt request, INA# is issued over adaptive interrupt scheme
#define TCR0_VETAG          0x20	// enable VLAN tag
#define TCR0_IPCK           0x10	// request IP  checksum calculation.
#define TCR0_UDPCK          0x08	// request UDP checksum calculation.
#define TCR0_TCPCK          0x04	// request TCP checksum calculation.
#define TCR0_JMBO           0x02	// indicate a jumbo packet in GMAC side
#define TCR0_CRC            0x01	// disable CRC generation

#define TCPLS_NORMAL        3
#define TCPLS_START         2
#define TCPLS_END           1
#define TCPLS_MED           0


// max transmit or receive buffer size
#define CB_RX_BUF_SIZE     2048UL	// max buffer size
					// NOTE: must be multiple of 4

#define CB_MAX_RD_NUM       512	// MAX # of RD
#define CB_MAX_TD_NUM       256	// MAX # of TD

#define CB_INIT_RD_NUM_3119 128	// init # of RD, for setup VT3119
#define CB_INIT_TD_NUM_3119 64	// init # of TD, for setup VT3119

#define CB_INIT_RD_NUM      128	// init # of RD, for setup default
#define CB_INIT_TD_NUM      64	// init # of TD, for setup default

// for 3119
#define CB_TD_RING_NUM      4	// # of TD rings.
#define CB_MAX_SEG_PER_PKT  7	// max data seg per packet (Tx)


/*
 *	If collisions excess 15 times , tx will abort, and
 *	if tx fifo underflow, tx will fail
 *	we should try to resend it
 */

#define CB_MAX_TX_ABORT_RETRY   3

/*
 *	Receive descriptor
 */

struct rdesc0 {
	u16 RSR;		/* Receive status */
	u16 len:14;		/* Received packet length */
	u16 reserved:1;
	u16 owner:1;		/* Who owns this buffer ? */
};

struct rdesc1 {
	u16 PQTAG;
	u8 CSM;
	u8 IPKT;
};

struct rx_desc {
	struct rdesc0 rdesc0;
	struct rdesc1 rdesc1;
	u32 pa_low;		/* Low 32 bit PCI address */
	u16 pa_high;		/* Next 16 bit PCI address (48 total) */
	u16 len:15;		/* Frame size */
	u16 inten:1;		/* Enable interrupt */
} __attribute__ ((__packed__));

/*
 *	Transmit descriptor
 */

struct tdesc0 {
	u16 TSR;		/* Transmit status register */
	u16 pktsize:14;		/* Size of frame */
	u16 reserved:1;
	u16 owner:1;		/* Who owns the buffer */
};

struct pqinf {			/* Priority queue info */
	u16 VID:12;
	u16 CFI:1;
	u16 priority:3;
} __attribute__ ((__packed__));

struct tdesc1 {
	struct pqinf pqinf;
	u8 TCR;
	u8 TCPLS:2;
	u8 reserved:2;
	u8 CMDZ:4;
} __attribute__ ((__packed__));

struct td_buf {
	u32 pa_low;
	u16 pa_high;
	u16 bufsize:14;	
	u16 reserved:1;
	u16 queue:1;
} __attribute__ ((__packed__));

struct tx_desc {
	struct tdesc0 tdesc0;
	struct tdesc1 tdesc1;
	struct td_buf td_buf[7];
};

struct velocity_rd_info {
	struct sk_buff *skb;
	dma_addr_t skb_dma;
};

/**
 *	alloc_rd_info		-	allocate an rd info block
 *
 *	Alocate and initialize a receive info structure used for keeping
 *	track of kernel side information related to each receive
 *	descriptor we are using
 */

static inline struct velocity_rd_info *alloc_rd_info(void)
{
	struct velocity_rd_info *ptr;
	if ((ptr = kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
		return NULL;
	else {
		memset(ptr, 0, sizeof(struct velocity_rd_info));
		return ptr;
	}
}

/*
 *	Used to track transmit side buffers.
 */

struct velocity_td_info {
	struct sk_buff *skb;
	u8 *buf;
	int nskb_dma;
	dma_addr_t skb_dma[7];
	dma_addr_t buf_dma;
};

enum {
	OWNED_BY_HOST = 0,
	OWNED_BY_NIC = 1
} velocity_owner;


/*
 *	MAC registers and macros.
 */


#define MCAM_SIZE           64
#define VCAM_SIZE           64
#define TX_QUEUE_NO         4

#define MAX_HW_MIB_COUNTER  32
#define VELOCITY_MIN_MTU    (1514-14)
#define VELOCITY_MAX_MTU    (9000)

/*
 *	Registers in the MAC
 */

#define MAC_REG_PAR         0x00	// physical address
#define MAC_REG_RCR         0x06
#define MAC_REG_TCR         0x07
#define MAC_REG_CR0_SET     0x08
#define MAC_REG_CR1_SET     0x09
#define MAC_REG_CR2_SET     0x0A
#define MAC_REG_CR3_SET     0x0B
#define MAC_REG_CR0_CLR     0x0C
#define MAC_REG_CR1_CLR     0x0D
#define MAC_REG_CR2_CLR     0x0E
#define MAC_REG_CR3_CLR     0x0F
#define MAC_REG_MAR         0x10
#define MAC_REG_CAM         0x10
#define MAC_REG_DEC_BASE_HI 0x18
#define MAC_REG_DBF_BASE_HI 0x1C
#define MAC_REG_ISR_CTL     0x20
#define MAC_REG_ISR_HOTMR   0x20
#define MAC_REG_ISR_TSUPTHR 0x20
#define MAC_REG_ISR_RSUPTHR 0x20
#define MAC_REG_ISR_CTL1    0x21
#define MAC_REG_TXE_SR      0x22
#define MAC_REG_RXE_SR      0x23
#define MAC_REG_ISR         0x24
#define MAC_REG_ISR0        0x24
#define MAC_REG_ISR1        0x25
#define MAC_REG_ISR2        0x26
#define MAC_REG_ISR3        0x27
#define MAC_REG_IMR         0x28
#define MAC_REG_IMR0        0x28
#define MAC_REG_IMR1        0x29
#define MAC_REG_IMR2        0x2A
#define MAC_REG_IMR3        0x2B
#define MAC_REG_TDCSR_SET   0x30
#define MAC_REG_RDCSR_SET   0x32
#define MAC_REG_TDCSR_CLR   0x34
#define MAC_REG_RDCSR_CLR   0x36
#define MAC_REG_RDBASE_LO   0x38
#define MAC_REG_RDINDX      0x3C
#define MAC_REG_TDBASE_LO   0x40
#define MAC_REG_RDCSIZE     0x50
#define MAC_REG_TDCSIZE     0x52
#define MAC_REG_TDINDX      0x54
#define MAC_REG_TDIDX0      0x54
#define MAC_REG_TDIDX1      0x56
#define MAC_REG_TDIDX2      0x58
#define MAC_REG_TDIDX3      0x5A
#define MAC_REG_PAUSE_TIMER 0x5C
#define MAC_REG_RBRDU       0x5E
#define MAC_REG_FIFO_TEST0  0x60
#define MAC_REG_FIFO_TEST1  0x64
#define MAC_REG_CAMADDR     0x68
#define MAC_REG_CAMCR       0x69
#define MAC_REG_GFTEST      0x6A
#define MAC_REG_FTSTCMD     0x6B
#define MAC_REG_MIICFG      0x6C
#define MAC_REG_MIISR       0x6D
#define MAC_REG_PHYSR0      0x6E
#define MAC_REG_PHYSR1      0x6F
#define MAC_REG_MIICR       0x70
#define MAC_REG_MIIADR      0x71
#define MAC_REG_MIIDATA     0x72
#define MAC_REG_SOFT_TIMER0 0x74
#define MAC_REG_SOFT_TIMER1 0x76
#define MAC_REG_CFGA        0x78
#define MAC_REG_CFGB        0x79
#define MAC_REG_CFGC        0x7A
#define MAC_REG_CFGD        0x7B
#define MAC_REG_DCFG0       0x7C
#define MAC_REG_DCFG1       0x7D
#define MAC_REG_MCFG0       0x7E
#define MAC_REG_MCFG1       0x7F

#define MAC_REG_TBIST       0x80
#define MAC_REG_RBIST       0x81
#define MAC_REG_PMCC        0x82
#define MAC_REG_STICKHW     0x83
#define MAC_REG_MIBCR       0x84
#define MAC_REG_EERSV       0x85
#define MAC_REG_REVID       0x86
#define MAC_REG_MIBREAD     0x88
#define MAC_REG_BPMA        0x8C
#define MAC_REG_EEWR_DATA   0x8C
#define MAC_REG_BPMD_WR     0x8F
#define MAC_REG_BPCMD       0x90
#define MAC_REG_BPMD_RD     0x91
#define MAC_REG_EECHKSUM    0x92
#define MAC_REG_EECSR       0x93
#define MAC_REG_EERD_DATA   0x94
#define MAC_REG_EADDR       0x96
#define MAC_REG_EMBCMD      0x97
#define MAC_REG_JMPSR0      0x98
#define MAC_REG_JMPSR1      0x99
#define MAC_REG_JMPSR2      0x9A
#define MAC_REG_JMPSR3      0x9B
#define MAC_REG_CHIPGSR     0x9C
#define MAC_REG_TESTCFG     0x9D
#define MAC_REG_DEBUG       0x9E
#define MAC_REG_CHIPGCR     0x9F
#define MAC_REG_WOLCR0_SET  0xA0
#define MAC_REG_WOLCR1_SET  0xA1
#define MAC_REG_PWCFG_SET   0xA2
#define MAC_REG_WOLCFG_SET  0xA3
#define MAC_REG_WOLCR0_CLR  0xA4
#define MAC_REG_WOLCR1_CLR  0xA5
#define MAC_REG_PWCFG_CLR   0xA6
#define MAC_REG_WOLCFG_CLR  0xA7
#define MAC_REG_WOLSR0_SET  0xA8
#define MAC_REG_WOLSR1_SET  0xA9
#define MAC_REG_WOLSR0_CLR  0xAC
#define MAC_REG_WOLSR1_CLR  0xAD
#define MAC_REG_PATRN_CRC0  0xB0
#define MAC_REG_PATRN_CRC1  0xB2
#define MAC_REG_PATRN_CRC2  0xB4
#define MAC_REG_PATRN_CRC3  0xB6
#define MAC_REG_PATRN_CRC4  0xB8
#define MAC_REG_PATRN_CRC5  0xBA
#define MAC_REG_PATRN_CRC6  0xBC
#define MAC_REG_PATRN_CRC7  0xBE
#define MAC_REG_BYTEMSK0_0  0xC0
#define MAC_REG_BYTEMSK0_1  0xC4
#define MAC_REG_BYTEMSK0_2  0xC8
#define MAC_REG_BYTEMSK0_3  0xCC
#define MAC_REG_BYTEMSK1_0  0xD0
#define MAC_REG_BYTEMSK1_1  0xD4
#define MAC_REG_BYTEMSK1_2  0xD8
#define MAC_REG_BYTEMSK1_3  0xDC
#define MAC_REG_BYTEMSK2_0  0xE0
#define MAC_REG_BYTEMSK2_1  0xE4
#define MAC_REG_BYTEMSK2_2  0xE8
#define MAC_REG_BYTEMSK2_3  0xEC
#define MAC_REG_BYTEMSK3_0  0xF0
#define MAC_REG_BYTEMSK3_1  0xF4
#define MAC_REG_BYTEMSK3_2  0xF8
#define MAC_REG_BYTEMSK3_3  0xFC

/*
 *	Bits in the RCR register
 */

#define RCR_AS              0x80
#define RCR_AP              0x40
#define RCR_AL              0x20
#define RCR_PROM            0x10
#define RCR_AB              0x08
#define RCR_AM              0x04
#define RCR_AR              0x02
#define RCR_SEP             0x01

/*
 *	Bits in the TCR register
 */

#define TCR_TB2BDIS         0x80
#define TCR_COLTMC1         0x08
#define TCR_COLTMC0         0x04