typhoon.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 620 行 · 第 1/2 页

 */
struct cmd_desc {
	u8  flags;
	u8  numDesc;
	u16 cmd;
#define TYPHOON_CMD_TX_ENABLE		__constant_cpu_to_le16(0x0001)
#define TYPHOON_CMD_TX_DISABLE		__constant_cpu_to_le16(0x0002)
#define TYPHOON_CMD_RX_ENABLE		__constant_cpu_to_le16(0x0003)
#define TYPHOON_CMD_RX_DISABLE		__constant_cpu_to_le16(0x0004)
#define TYPHOON_CMD_SET_RX_FILTER	__constant_cpu_to_le16(0x0005)
#define TYPHOON_CMD_READ_STATS		__constant_cpu_to_le16(0x0007)
#define TYPHOON_CMD_XCVR_SELECT		__constant_cpu_to_le16(0x0013)
#define TYPHOON_CMD_SET_MAX_PKT_SIZE	__constant_cpu_to_le16(0x001a)
#define TYPHOON_CMD_READ_MEDIA_STATUS	__constant_cpu_to_le16(0x001b)
#define TYPHOON_CMD_GOTO_SLEEP		__constant_cpu_to_le16(0x0023)
#define TYPHOON_CMD_SET_MULTICAST_HASH	__constant_cpu_to_le16(0x0025)
#define TYPHOON_CMD_SET_MAC_ADDRESS	__constant_cpu_to_le16(0x0026)
#define TYPHOON_CMD_READ_MAC_ADDRESS	__constant_cpu_to_le16(0x0027)
#define TYPHOON_CMD_VLAN_TYPE_WRITE	__constant_cpu_to_le16(0x002b)
#define TYPHOON_CMD_CREATE_SA		__constant_cpu_to_le16(0x0034)
#define TYPHOON_CMD_DELETE_SA		__constant_cpu_to_le16(0x0035)
#define TYPHOON_CMD_READ_VERSIONS	__constant_cpu_to_le16(0x0043)
#define TYPHOON_CMD_IRQ_COALESCE_CTRL	__constant_cpu_to_le16(0x0045)
#define TYPHOON_CMD_ENABLE_WAKE_EVENTS	__constant_cpu_to_le16(0x0049)
#define TYPHOON_CMD_SET_OFFLOAD_TASKS	__constant_cpu_to_le16(0x004f)
#define TYPHOON_CMD_HELLO_RESP		__constant_cpu_to_le16(0x0057)
#define TYPHOON_CMD_HALT		__constant_cpu_to_le16(0x005d)
#define TYPHOON_CMD_READ_IPSEC_INFO	__constant_cpu_to_le16(0x005e)
#define TYPHOON_CMD_GET_IPSEC_ENABLE	__constant_cpu_to_le16(0x0067)
#define TYPHOON_CMD_GET_CMD_LVL		__constant_cpu_to_le16(0x0069)
	u16 seqNo;
	u16 parm1;
	u32 parm2;
	u32 parm3;
} __attribute__ ((packed));

/* The Typhoon response descriptor, see command descriptor for details
 */
struct resp_desc {
	u8  flags;
	u8  numDesc;
	u16 cmd;
	u16 seqNo;
	u16 parm1;
	u32 parm2;
	u32 parm3;
} __attribute__ ((packed));

#define INIT_COMMAND_NO_RESPONSE(x, command)				\
	do { struct cmd_desc *_ptr = (x);				\
		memset(_ptr, 0, sizeof(struct cmd_desc));		\
		_ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID;	\
		_ptr->cmd = command;					\
	} while(0)

/* We set seqNo to 1 if we're expecting a response from this command */
#define INIT_COMMAND_WITH_RESPONSE(x, command)				\
	do { struct cmd_desc *_ptr = (x);				\
		memset(_ptr, 0, sizeof(struct cmd_desc));		\
		_ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC;	\
		_ptr->flags |= TYPHOON_DESC_VALID; 			\
		_ptr->cmd = command;					\
		_ptr->seqNo = 1;					\
	} while(0)

/* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1)
 */
#define TYPHOON_RX_FILTER_DIRECTED	__constant_cpu_to_le16(0x0001)
#define TYPHOON_RX_FILTER_ALL_MCAST	__constant_cpu_to_le16(0x0002)
#define TYPHOON_RX_FILTER_BROADCAST	__constant_cpu_to_le16(0x0004)
#define TYPHOON_RX_FILTER_PROMISCOUS	__constant_cpu_to_le16(0x0008)
#define TYPHOON_RX_FILTER_MCAST_HASH	__constant_cpu_to_le16(0x0010)

/* TYPHOON_CMD_READ_STATS response format
 */
struct stats_resp {
	u8  flags;
	u8  numDesc;
	u16 cmd;
	u16 seqNo;
	u16 unused;
	u32 txPackets;
	u64 txBytes;
	u32 txDeferred;
	u32 txLateCollisions;
	u32 txCollisions;
	u32 txCarrierLost;
	u32 txMultipleCollisions;
	u32 txExcessiveCollisions;
	u32 txFifoUnderruns;
	u32 txMulticastTxOverflows;
	u32 txFiltered;
	u32 rxPacketsGood;
	u64 rxBytesGood;
	u32 rxFifoOverruns;
	u32 BadSSD;
	u32 rxCrcErrors;
	u32 rxOversized;
	u32 rxBroadcast;
	u32 rxMulticast;
	u32 rxOverflow;
	u32 rxFiltered;
	u32 linkStatus;
#define TYPHOON_LINK_STAT_MASK		__constant_cpu_to_le32(0x00000001)
#define TYPHOON_LINK_GOOD		__constant_cpu_to_le32(0x00000001)
#define TYPHOON_LINK_BAD		__constant_cpu_to_le32(0x00000000)
#define TYPHOON_LINK_SPEED_MASK		__constant_cpu_to_le32(0x00000002)
#define TYPHOON_LINK_100MBPS		__constant_cpu_to_le32(0x00000002)
#define TYPHOON_LINK_10MBPS		__constant_cpu_to_le32(0x00000000)
#define TYPHOON_LINK_DUPLEX_MASK	__constant_cpu_to_le32(0x00000004)
#define TYPHOON_LINK_FULL_DUPLEX	__constant_cpu_to_le32(0x00000004)
#define TYPHOON_LINK_HALF_DUPLEX	__constant_cpu_to_le32(0x00000000)
	u32 unused2;
	u32 unused3;
} __attribute__ ((packed));

/* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1)
 */
#define TYPHOON_XCVR_10HALF	__constant_cpu_to_le16(0x0000)
#define TYPHOON_XCVR_10FULL	__constant_cpu_to_le16(0x0001)
#define TYPHOON_XCVR_100HALF	__constant_cpu_to_le16(0x0002)
#define TYPHOON_XCVR_100FULL	__constant_cpu_to_le16(0x0003)
#define TYPHOON_XCVR_AUTONEG	__constant_cpu_to_le16(0x0004)

/* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1)
 */
#define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE	__constant_cpu_to_le16(0x0004)
#define TYPHOON_MEDIA_STAT_COLLISION_DETECT	__constant_cpu_to_le16(0x0010)
#define TYPHOON_MEDIA_STAT_CARRIER_SENSE	__constant_cpu_to_le16(0x0020)
#define TYPHOON_MEDIA_STAT_POLARITY_REV		__constant_cpu_to_le16(0x0400)
#define TYPHOON_MEDIA_STAT_NO_LINK		__constant_cpu_to_le16(0x0800)

/* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1)
 */
#define TYPHOON_MCAST_HASH_DISABLE	__constant_cpu_to_le16(0x0000)
#define TYPHOON_MCAST_HASH_ENABLE	__constant_cpu_to_le16(0x0001)
#define TYPHOON_MCAST_HASH_SET		__constant_cpu_to_le16(0x0002)

/* TYPHOON_CMD_CREATE_SA descriptor and settings
 */
struct sa_descriptor {
	u8  flags;
	u8  numDesc;
	u16 cmd;
	u16 seqNo;
	u16 mode;
#define TYPHOON_SA_MODE_NULL		__constant_cpu_to_le16(0x0000)
#define TYPHOON_SA_MODE_AH		__constant_cpu_to_le16(0x0001)
#define TYPHOON_SA_MODE_ESP		__constant_cpu_to_le16(0x0002)
	u8  hashFlags;
#define TYPHOON_SA_HASH_ENABLE		0x01
#define TYPHOON_SA_HASH_SHA1		0x02
#define TYPHOON_SA_HASH_MD5		0x04
	u8  direction;
#define TYPHOON_SA_DIR_RX		0x00
#define TYPHOON_SA_DIR_TX		0x01
	u8  encryptionFlags;
#define TYPHOON_SA_ENCRYPT_ENABLE	0x01
#define TYPHOON_SA_ENCRYPT_DES		0x02
#define TYPHOON_SA_ENCRYPT_3DES		0x00
#define TYPHOON_SA_ENCRYPT_3DES_2KEY	0x00
#define TYPHOON_SA_ENCRYPT_3DES_3KEY	0x04
#define TYPHOON_SA_ENCRYPT_CBC		0x08
#define TYPHOON_SA_ENCRYPT_ECB		0x00
	u8  specifyIndex;
#define TYPHOON_SA_SPECIFY_INDEX	0x01
#define TYPHOON_SA_GENERATE_INDEX	0x00
	u32 SPI;
	u32 destAddr;
	u32 destMask;
	u8  integKey[20];
	u8  confKey[24];
	u32 index;
	u32 unused;
	u32 unused2;
} __attribute__ ((packed));

/* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx))
 * This is all for IPv4.
 */
#define TYPHOON_OFFLOAD_TCP_CHKSUM	__constant_cpu_to_le32(0x00000002)
#define TYPHOON_OFFLOAD_UDP_CHKSUM	__constant_cpu_to_le32(0x00000004)
#define TYPHOON_OFFLOAD_IP_CHKSUM	__constant_cpu_to_le32(0x00000008)
#define TYPHOON_OFFLOAD_IPSEC		__constant_cpu_to_le32(0x00000010)
#define TYPHOON_OFFLOAD_BCAST_THROTTLE	__constant_cpu_to_le32(0x00000020)
#define TYPHOON_OFFLOAD_DHCP_PREVENT	__constant_cpu_to_le32(0x00000040)
#define TYPHOON_OFFLOAD_VLAN		__constant_cpu_to_le32(0x00000080)
#define TYPHOON_OFFLOAD_FILTERING	__constant_cpu_to_le32(0x00000100)
#define TYPHOON_OFFLOAD_TCP_SEGMENT	__constant_cpu_to_le32(0x00000200)

/* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1)
 */
#define TYPHOON_WAKE_MAGIC_PKT		__constant_cpu_to_le16(0x01)
#define TYPHOON_WAKE_LINK_EVENT		__constant_cpu_to_le16(0x02)
#define TYPHOON_WAKE_ICMP_ECHO		__constant_cpu_to_le16(0x04)
#define TYPHOON_WAKE_ARP		__constant_cpu_to_le16(0x08)

/* These are used to load the firmware image on the NIC
 */
struct typhoon_file_header {
	u8  tag[8];
	u32 version;
	u32 numSections;
	u32 startAddr;
	u32 hmacDigest[5];
} __attribute__ ((packed));

struct typhoon_section_header {
	u32 len;
	u16 checksum;
	u16 reserved;
	u32 startAddr;
} __attribute__ ((packed));

/* The Typhoon Register offsets
 */
#define TYPHOON_REG_SOFT_RESET			0x00
#define TYPHOON_REG_INTR_STATUS			0x04
#define TYPHOON_REG_INTR_ENABLE			0x08
#define TYPHOON_REG_INTR_MASK			0x0c
#define TYPHOON_REG_SELF_INTERRUPT		0x10
#define TYPHOON_REG_HOST2ARM7			0x14
#define TYPHOON_REG_HOST2ARM6			0x18
#define TYPHOON_REG_HOST2ARM5			0x1c
#define TYPHOON_REG_HOST2ARM4			0x20
#define TYPHOON_REG_HOST2ARM3			0x24
#define TYPHOON_REG_HOST2ARM2			0x28
#define TYPHOON_REG_HOST2ARM1			0x2c
#define TYPHOON_REG_HOST2ARM0			0x30
#define TYPHOON_REG_ARM2HOST3			0x34
#define TYPHOON_REG_ARM2HOST2			0x38
#define TYPHOON_REG_ARM2HOST1			0x3c
#define TYPHOON_REG_ARM2HOST0			0x40

#define TYPHOON_REG_BOOT_DATA_LO		TYPHOON_REG_HOST2ARM5
#define TYPHOON_REG_BOOT_DATA_HI		TYPHOON_REG_HOST2ARM4
#define TYPHOON_REG_BOOT_DEST_ADDR		TYPHOON_REG_HOST2ARM3
#define TYPHOON_REG_BOOT_CHECKSUM		TYPHOON_REG_HOST2ARM2
#define TYPHOON_REG_BOOT_LENGTH			TYPHOON_REG_HOST2ARM1

#define TYPHOON_REG_DOWNLOAD_BOOT_ADDR		TYPHOON_REG_HOST2ARM1
#define TYPHOON_REG_DOWNLOAD_HMAC_0		TYPHOON_REG_HOST2ARM2
#define TYPHOON_REG_DOWNLOAD_HMAC_1		TYPHOON_REG_HOST2ARM3
#define TYPHOON_REG_DOWNLOAD_HMAC_2		TYPHOON_REG_HOST2ARM4
#define TYPHOON_REG_DOWNLOAD_HMAC_3		TYPHOON_REG_HOST2ARM5
#define TYPHOON_REG_DOWNLOAD_HMAC_4		TYPHOON_REG_HOST2ARM6

#define TYPHOON_REG_BOOT_RECORD_ADDR_HI		TYPHOON_REG_HOST2ARM2
#define TYPHOON_REG_BOOT_RECORD_ADDR_LO		TYPHOON_REG_HOST2ARM1

#define TYPHOON_REG_TX_LO_READY			TYPHOON_REG_HOST2ARM3
#define TYPHOON_REG_CMD_READY			TYPHOON_REG_HOST2ARM2
#define TYPHOON_REG_TX_HI_READY			TYPHOON_REG_HOST2ARM1

#define TYPHOON_REG_COMMAND			TYPHOON_REG_HOST2ARM0
#define TYPHOON_REG_HEARTBEAT			TYPHOON_REG_ARM2HOST3
#define TYPHOON_REG_STATUS			TYPHOON_REG_ARM2HOST0

/* 3XP Reset values (TYPHOON_REG_SOFT_RESET)
 */
#define TYPHOON_RESET_ALL	0x7f
#define TYPHOON_RESET_NONE	0x00

/* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK})
 *
 * Some of these came from OpenBSD, as the 3Com docs have it wrong
 * (INTR_SELF) or don't list it at all (INTR_*_ABORT)
 *
 * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq
 * about every 8ms, so don't do it.
 */
#define TYPHOON_INTR_HOST_INT		0x00000001
#define TYPHOON_INTR_ARM2HOST0		0x00000002
#define TYPHOON_INTR_ARM2HOST1		0x00000004
#define TYPHOON_INTR_ARM2HOST2		0x00000008
#define TYPHOON_INTR_ARM2HOST3		0x00000010
#define TYPHOON_INTR_DMA0		0x00000020
#define TYPHOON_INTR_DMA1		0x00000040
#define TYPHOON_INTR_DMA2		0x00000080
#define TYPHOON_INTR_DMA3		0x00000100
#define TYPHOON_INTR_MASTER_ABORT	0x00000200
#define TYPHOON_INTR_TARGET_ABORT	0x00000400
#define TYPHOON_INTR_SELF		0x00000800
#define TYPHOON_INTR_RESERVED		0xfffff000

#define TYPHOON_INTR_BOOTCMD		TYPHOON_INTR_ARM2HOST0

#define TYPHOON_INTR_ENABLE_ALL		0xffffffef
#define TYPHOON_INTR_ALL		0xffffffff
#define TYPHOON_INTR_NONE		0x00000000

/* The commands for the 3XP chip (TYPHOON_REG_COMMAND)
 */
#define TYPHOON_BOOTCMD_BOOT			0x00
#define TYPHOON_BOOTCMD_WAKEUP			0xfa
#define TYPHOON_BOOTCMD_DNLD_COMPLETE		0xfb
#define TYPHOON_BOOTCMD_SEG_AVAILABLE		0xfc
#define TYPHOON_BOOTCMD_RUNTIME_IMAGE		0xfd
#define TYPHOON_BOOTCMD_REG_BOOT_RECORD		0xff

/* 3XP Status values (TYPHOON_REG_STATUS)
 */
#define TYPHOON_STATUS_WAITING_FOR_BOOT		0x07
#define TYPHOON_STATUS_SECOND_INIT		0x08
#define TYPHOON_STATUS_RUNNING			0x09
#define TYPHOON_STATUS_WAITING_FOR_HOST		0x0d
#define TYPHOON_STATUS_WAITING_FOR_SEGMENT	0x10
#define TYPHOON_STATUS_SLEEPING			0x11
#define TYPHOON_STATUS_HALTED			0x14