mv643xx_eth.h

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#ifndef __MV64340_ETH_H__
#define __MV64340_ETH_H__

#include <linux/version.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>

#include <linux/mv643xx.h>

#define	BIT0	0x00000001
#define	BIT1	0x00000002
#define	BIT2	0x00000004
#define	BIT3	0x00000008
#define	BIT4	0x00000010
#define	BIT5	0x00000020
#define	BIT6	0x00000040
#define	BIT7	0x00000080
#define	BIT8	0x00000100
#define	BIT9	0x00000200
#define	BIT10	0x00000400
#define	BIT11	0x00000800
#define	BIT12	0x00001000
#define	BIT13	0x00002000
#define	BIT14	0x00004000
#define	BIT15	0x00008000
#define	BIT16	0x00010000
#define	BIT17	0x00020000
#define	BIT18	0x00040000
#define	BIT19	0x00080000
#define	BIT20	0x00100000
#define	BIT21	0x00200000
#define	BIT22	0x00400000
#define	BIT23	0x00800000
#define	BIT24	0x01000000
#define	BIT25	0x02000000
#define	BIT26	0x04000000
#define	BIT27	0x08000000
#define	BIT28	0x10000000
#define	BIT29	0x20000000
#define	BIT30	0x40000000
#define	BIT31	0x80000000

/*
 *  The first part is the high level driver of the gigE ethernet ports.
 */

#define ETH_PORT0_IRQ_NUM 48			/* main high register, bit0 */
#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1	/* main high register, bit1 */
#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2	/* main high register, bit1 */

/* Checksum offload for Tx works */
#define  MV64340_CHECKSUM_OFFLOAD_TX
#define	 MV64340_NAPI
#define	 MV64340_TX_FAST_REFILL
#undef	 MV64340_COAL

/* 
 * Number of RX / TX descriptors on RX / TX rings.
 * Note that allocating RX descriptors is done by allocating the RX
 * ring AND a preallocated RX buffers (skb's) for each descriptor.
 * The TX descriptors only allocates the TX descriptors ring,
 * with no pre allocated TX buffers (skb's are allocated by higher layers.
 */

/* Default TX ring size is 1000 descriptors */
#define MV64340_TX_QUEUE_SIZE 1000

/* Default RX ring size is 400 descriptors */
#define MV64340_RX_QUEUE_SIZE 400

#define MV64340_TX_COAL 100
#ifdef MV64340_COAL
#define MV64340_RX_COAL 100
#endif


/*
 * The second part is the low level driver of the gigE ethernet ports.   *
 */


/*
 * Header File for : MV-643xx network interface header 
 *
 * DESCRIPTION:
 *       This header file contains macros typedefs and function declaration for
 *       the Marvell Gig Bit Ethernet Controller. 
 *
 * DEPENDENCIES:
 *       None.
 *
 */

/* Default port configuration value */
#define PORT_CONFIG_VALUE                       \
             ETH_UNICAST_NORMAL_MODE		|   \
             ETH_DEFAULT_RX_QUEUE_0		|   \
             ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
             ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
             ETH_RECEIVE_BC_IF_IP		|   \
             ETH_RECEIVE_BC_IF_ARP 		|   \
             ETH_CAPTURE_TCP_FRAMES_DIS		|   \
             ETH_CAPTURE_UDP_FRAMES_DIS		|   \
             ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
             ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
             ETH_DEFAULT_RX_BPDU_QUEUE_0

/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE		\
             ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
             ETH_PARTITION_DISABLE


/* Default sdma control value */
#define PORT_SDMA_CONFIG_VALUE			\
			 ETH_RX_BURST_SIZE_16_64BIT 	|	\
			 GT_ETH_IPG_INT_RX(0) 		|	\
			 ETH_TX_BURST_SIZE_16_64BIT;

#define GT_ETH_IPG_INT_RX(value)                \
            ((value & 0x3fff) << 8)

/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE		\
			ETH_FORCE_LINK_PASS 			|	\
			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL 	|	\
			ETH_ADV_SYMMETRIC_FLOW_CTRL 		|	\
			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 	|	\
			ETH_FORCE_BP_MODE_NO_JAM 		|	\
			BIT9 					|	\
			ETH_DO_NOT_FORCE_LINK_FAIL 		|	\
			ETH_RETRANSMIT_16_ATTEMPTS 		|	\
			ETH_ENABLE_AUTO_NEG_SPEED_GMII	 	|	\
			ETH_DTE_ADV_0 				|	\
			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
			ETH_AUTO_NEG_NO_CHANGE 			|	\
			ETH_MAX_RX_PACKET_9700BYTE 		|	\
			ETH_CLR_EXT_LOOPBACK 			|	\
			ETH_SET_FULL_DUPLEX_MODE 		|	\
			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX

#define RX_BUFFER_MAX_SIZE  0x4000000
#define TX_BUFFER_MAX_SIZE  0x4000000

/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR	    0
#define REJECT_MAC_ADDR	    1

/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET				0x2

/* Gigabit Ethernet Unit Global Registers */

/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
#define ETH_MIB_FRAMES_64_OCTETS           0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
#define ETH_MIB_GOOD_FRAMES_SENT           0x40
#define ETH_MIB_EXCESSIVE_COLLISION        0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT                    0x54
#define ETH_MIB_GOOD_FC_RECEIVED           0x58
#define ETH_MIB_BAD_FC_RECEIVED            0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED         0x60
#define ETH_MIB_FRAGMENTS_RECEIVED         0x64
#define ETH_MIB_OVERSIZE_RECEIVED          0x68
#define ETH_MIB_JABBER_RECEIVED            0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR          0x70
#define ETH_MIB_BAD_CRC_EVENT              0x74
#define ETH_MIB_COLLISION                  0x78
#define ETH_MIB_LATE_COLLISION             0x7c

/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII                          0
#define ETH_INTERFACE_PCM                               BIT0
#define ETH_LINK_IS_DOWN                                0
#define ETH_LINK_IS_UP                                  BIT1
#define ETH_PORT_AT_HALF_DUPLEX                         0
#define ETH_PORT_AT_FULL_DUPLEX                         BIT2
#define ETH_RX_FLOW_CTRL_DISABLED                       0
#define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
#define ETH_GMII_SPEED_100_10                           0
#define ETH_GMII_SPEED_1000                             BIT4
#define ETH_MII_SPEED_10                                0
#define ETH_MII_SPEED_100                               BIT5
#define ETH_NO_TX                                       0
#define ETH_TX_IN_PROGRESS                              BIT7
#define ETH_BYPASS_NO_ACTIVE                            0
#define ETH_BYPASS_ACTIVE                               BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE                 0
#define ETH_PORT_AT_PARTITION_STATE                     BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
#define ETH_PORT_TX_FIFO_EMPTY                          BIT10


/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE                         0
#define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
#define ETH_DEFAULT_RX_QUEUE_0                          0
#define ETH_DEFAULT_RX_QUEUE_1                          BIT1
#define ETH_DEFAULT_RX_QUEUE_2                          BIT2
#define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4                          BIT3
#define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
#define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
#define ETH_RECEIVE_BC_IF_IP                            0
#define ETH_REJECT_BC_IF_IP                             BIT8
#define ETH_RECEIVE_BC_IF_ARP                           0
#define ETH_REJECT_BC_IF_ARP                            BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS                      0
#define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS                      0
#define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
#define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
#define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)


/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN                                 BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
#define ETH_PARTITION_DISABLE                           0
#define ETH_PARTITION_ENABLE                            BIT2


/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE                              BIT0
#define ETH_QUEUE_1_ENABLE                              BIT1
#define ETH_QUEUE_2_ENABLE                              BIT2
#define ETH_QUEUE_3_ENABLE                              BIT3
#define ETH_QUEUE_4_ENABLE                              BIT4
#define ETH_QUEUE_5_ENABLE                              BIT5
#define ETH_QUEUE_6_ENABLE                              BIT6
#define ETH_QUEUE_7_ENABLE                              BIT7
#define ETH_QUEUE_0_DISABLE                             BIT8
#define ETH_QUEUE_1_DISABLE                             BIT9
#define ETH_QUEUE_2_DISABLE                             BIT10
#define ETH_QUEUE_3_DISABLE                             BIT11
#define ETH_QUEUE_4_DISABLE                             BIT12
#define ETH_QUEUE_5_DISABLE                             BIT13
#define ETH_QUEUE_6_DISABLE                             BIT14
#define ETH_QUEUE_7_DISABLE                             BIT15


/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB                                        BIT0
#define ETH_RX_BURST_SIZE_1_64BIT                       0
#define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
#define ETH_RX_BURST_SIZE_4_64BIT                       BIT2