dl2k.h

Linux Kernel 2.6.9 for OMAP1710

enum _mii_bmsr {
	MII_BMSR_100BT4 = 0x8000,
	MII_BMSR_100BX_FD = 0x4000,
	MII_BMSR_100BX_HD = 0x2000,
	MII_BMSR_10BT_FD = 0x1000,
	MII_BMSR_10BT_HD = 0x0800,
	MII_BMSR_100BT2_FD = 0x0400,
	MII_BMSR_100BT2_HD = 0x0200,
	MII_BMSR_EXT_STATUS = 0x0100,
	MII_BMSR_PREAMBLE_SUPP = 0x0040,
	MII_BMSR_AN_COMPLETE = 0x0020,
	MII_BMSR_REMOTE_FAULT = 0x0010,
	MII_BMSR_AN_ABILITY = 0x0008,
	MII_BMSR_LINK_STATUS = 0x0004,
	MII_BMSR_JABBER_DETECT = 0x0002,
	MII_BMSR_EXT_CAP = 0x0001,
};

/* ANAR */
typedef union t_MII_ANAR {
	u16 image;
	struct {
		u16 selector:5;	// bit 4:0
		u16 media_10BT_HD:1;	// bit 5
		u16 media_10BT_FD:1;	// bit 6
		u16 media_100BX_HD:1;	// bit 7
		u16 media_100BX_FD:1;	// bit 8
		u16 media_100BT4:1;	// bit 9
		u16 pause:1;	// bit 10
		u16 asymmetric:1;	// bit 11
		u16 _bit12:1;	// bit 12
		u16 remote_fault:1;	// bit 13
		u16 _bit14:1;	// bit 14
		u16 next_page:1;	// bit 15
	} bits;
} ANAR_t, *PANAR_t;

enum _mii_anar {
	MII_ANAR_NEXT_PAGE = 0x8000,
	MII_ANAR_REMOTE_FAULT = 0x4000,
	MII_ANAR_ASYMMETRIC = 0x0800,
	MII_ANAR_PAUSE = 0x0400,
	MII_ANAR_100BT4 = 0x0200,
	MII_ANAR_100BX_FD = 0x0100,
	MII_ANAR_100BX_HD = 0x0080,
	MII_ANAR_10BT_FD = 0x0020,
	MII_ANAR_10BT_HD = 0x0010,
	MII_ANAR_SELECTOR = 0x001f,
	MII_IEEE8023_CSMACD = 0x0001,
};

/* ANLPAR */
typedef union t_MII_ANLPAR {
	u16 image;
	struct {
		u16 selector:5;	// bit 4:0
		u16 media_10BT_HD:1;	// bit 5
		u16 media_10BT_FD:1;	// bit 6
		u16 media_100BX_HD:1;	// bit 7
		u16 media_100BX_FD:1;	// bit 8
		u16 media_100BT4:1;	// bit 9
		u16 pause:1;	// bit 10
		u16 asymmetric:1;	// bit 11
		u16 _bit12:1;	// bit 12
		u16 remote_fault:1;	// bit 13
		u16 _bit14:1;	// bit 14
		u16 next_page:1;	// bit 15
	} bits;
} ANLPAR_t, *PANLPAR_t;

enum _mii_anlpar {
	MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
	MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
	MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
	MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
	MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
	MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
	MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
	MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
	MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
	MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
};

/* Auto-Negotiation Expansion Register */
typedef union t_MII_ANER {
	u16 image;
	struct {
		u16 lp_negotiable:1;	// bit 0
		u16 page_received:1;	// bit 1
		u16 nextpagable:1;	// bit 2
		u16 lp_nextpagable:1;	// bit 3
		u16 pdetect_fault:1;	// bit 4
		u16 _bit15_5:11;	// bit 15:5
	} bits;
} ANER_t, *PANER_t;

enum _mii_aner {
	MII_ANER_PAR_DETECT_FAULT = 0x0010,
	MII_ANER_LP_NEXTPAGABLE = 0x0008,
	MII_ANER_NETXTPAGABLE = 0x0004,
	MII_ANER_PAGE_RECEIVED = 0x0002,
	MII_ANER_LP_NEGOTIABLE = 0x0001,
};

/* MASTER-SLAVE Control Register */
typedef union t_MII_MSCR {
	u16 image;
	struct {
		u16 _bit_7_0:8;	// bit 7:0
		u16 media_1000BT_HD:1;	// bit 8
		u16 media_1000BT_FD:1;	// bit 9
		u16 port_type:1;	// bit 10
		u16 cfg_value:1;	// bit 11
		u16 cfg_enable:1;	// bit 12
		u16 test_mode:3;	// bit 15:13
	} bits;
} MSCR_t, *PMSCR_t;

enum _mii_mscr {
	MII_MSCR_TEST_MODE = 0xe000,
	MII_MSCR_CFG_ENABLE = 0x1000,
	MII_MSCR_CFG_VALUE = 0x0800,
	MII_MSCR_PORT_VALUE = 0x0400,
	MII_MSCR_1000BT_FD = 0x0200,
	MII_MSCR_1000BT_HD = 0X0100,
};

/* MASTER-SLAVE Status Register */
typedef union t_MII_MSSR {
	u16 image;
	struct {
		u16 idle_err_count:8;	// bit 7:0
		u16 _bit_9_8:2;	// bit 9:8
		u16 lp_1000BT_HD:1;	// bit 10
		u16 lp_1000BT_FD:1;	// bit 11
		u16 remote_rcv_status:1;	// bit 12
		u16 local_rcv_status:1;	// bit 13
		u16 cfg_resolution:1;	// bit 14
		u16 cfg_fault:1;	// bit 15
	} bits;
} MSSR_t, *PMSSR_t;

enum _mii_mssr {
	MII_MSSR_CFG_FAULT = 0x8000,
	MII_MSSR_CFG_RES = 0x4000,
	MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
	MII_MSSR_REMOTE_RCVR = 0x1000,
	MII_MSSR_LP_1000BT_HD = 0x0800,
	MII_MSSR_LP_1000BT_FD = 0x0400,
	MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
};

/* IEEE Extened Status Register */
typedef union t_MII_ESR {
	u16 image;
	struct {
		u16 _bit_11_0:12;	// bit 11:0
		u16 media_1000BT_HD:2;	// bit 12
		u16 media_1000BT_FD:1;	// bit 13
		u16 media_1000BX_HD:1;	// bit 14
		u16 media_1000BX_FD:1;	// bit 15
	} bits;
} ESR_t, *PESR_t;

enum _mii_esr {
	MII_ESR_1000BX_FD = 0x8000,
	MII_ESR_1000BX_HD = 0x4000,
	MII_ESR_1000BT_FD = 0x2000,
	MII_ESR_1000BT_HD = 0x1000,
};
/* PHY Specific Control Register */
typedef union t_MII_PHY_SCR {
	u16 image;
	struct {
		u16 disable_jabber:1;	// bit 0
		u16 polarity_reversal:1;	// bit 1
		u16 SEQ_test:1;	// bit 2
		u16 _bit_3:1;	// bit 3
		u16 disable_CLK125:1;	// bit 4
		u16 mdi_crossover_mode:2;	// bit 6:5
		u16 enable_ext_dist:1;	// bit 7
		u16 _bit_8_9:2;	// bit 9:8
		u16 force_link:1;	// bit 10
		u16 assert_CRS:1;	// bit 11
		u16 rcv_fifo_depth:2;	// bit 13:12
		u16 xmit_fifo_depth:2;	// bit 15:14
	} bits;
} PHY_SCR_t, *PPHY_SCR_t;

typedef enum t_MII_ADMIN_STATUS {
	adm_reset,
	adm_operational,
	adm_loopback,
	adm_power_down,
	adm_isolate
} MII_ADMIN_t, *PMII_ADMIN_t;

/* Physical Coding Sublayer Management (PCS) */
/* PCS control and status registers bitmap as the same as MII */
/* PCS Extended Status register bitmap as the same as MII */
/* PCS ANAR */
typedef union t_PCS_ANAR {
	u16 image;
	struct {
		u16 _bit_4_0:5;		// bit 4:0
		u16 full_duplex:1;	// bit 5
		u16 half_duplex:1;	// bit 6
		u16 asymmetric:1;	// bit 7
		u16 pause:1;		// bit 8
		u16 _bit_11_9:3;	// bit 11:9
		u16 remote_fault:2;	// bit 13:12
		u16 _bit_14:1;		// bit 14
		u16 next_page:1;	// bit 15
	} bits;
} ANAR_PCS_t, *PANAR_PCS_t;

enum _pcs_anar {
	PCS_ANAR_NEXT_PAGE = 0x8000,
	PCS_ANAR_REMOTE_FAULT = 0x3000,
	PCS_ANAR_ASYMMETRIC = 0x0100,
	PCS_ANAR_PAUSE = 0x0080,
	PCS_ANAR_HALF_DUPLEX = 0x0040,
	PCS_ANAR_FULL_DUPLEX = 0x0020,
};
/* PCS ANLPAR */
typedef union t_PCS_ANLPAR {
	u16 image;
	struct {
		u16 _bit_4_0:5;		// bit 4:0
		u16 full_duplex:1;	// bit 5
		u16 half_duplex:1;	// bit 6
		u16 asymmetric:1;	// bit 7
		u16 pause:1;		// bit 8
		u16 _bit_11_9:3;	// bit 11:9
		u16 remote_fault:2;	// bit 13:12
		u16 _bit_14:1;		// bit 14
		u16 next_page:1;	// bit 15
	} bits;
} ANLPAR_PCS_t, *PANLPAR_PCS_t;

enum _pcs_anlpar {
	PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, 
	PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
	PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
	PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
	PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
	PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
};

typedef struct t_SROM {
	u16 config_param;	/* 0x00 */
	u16 asic_ctrl;		/* 0x02 */
	u16 sub_vendor_id;	/* 0x04 */
	u16 sub_system_id;	/* 0x06 */
	u16 reserved1[12];	/* 0x08-0x1f */
	u8 mac_addr[6];		/* 0x20-0x25 */
	u8 reserved2[10];	/* 0x26-0x2f */
	u8 sib[204];		/* 0x30-0xfb */
	u32 crc;		/* 0xfc-0xff */
} SROM_t, *PSROM_t;

/* Ioctl custom data */
struct ioctl_data {
	char signature[10];
	int cmd;
	int len;
	char *data;
};

struct mii_data {
	__u16 reserved;
	__u16 reg_num;
	__u16 in_value;
	__u16 out_value;
};

/* The Rx and Tx buffer descriptors. */
struct netdev_desc {
	u64 next_desc;
	u64 status;
	u64 fraginfo;
};

#define PRIV_ALIGN	15	/* Required alignment mask */
/* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
   within the structure. */
struct netdev_private {
	/* Descriptor rings first for alignment. */
	struct netdev_desc *rx_ring;
	struct netdev_desc *tx_ring;
	struct sk_buff *rx_skbuff[RX_RING_SIZE];
	struct sk_buff *tx_skbuff[TX_RING_SIZE];
	dma_addr_t tx_ring_dma;
	dma_addr_t rx_ring_dma;
	struct pci_dev *pdev;
	spinlock_t tx_lock;
	spinlock_t rx_lock;
	struct net_device_stats stats;
	unsigned int rx_buf_sz;		/* Based on MTU+slack. */
	unsigned int speed;		/* Operating speed */
	unsigned int vlan;		/* VLAN Id */
	unsigned int chip_id;		/* PCI table chip id */
	unsigned int rx_coalesce; 	/* Maximum frames each RxDMAComplete intr */
	unsigned int rx_timeout; 	/* Wait time between RxDMAComplete intr */
	unsigned int tx_coalesce;	/* Maximum frames each tx interrupt */
	unsigned int full_duplex:1;	/* Full-duplex operation requested. */
	unsigned int an_enable:2;	/* Auto-Negotiated Enable */
	unsigned int jumbo:1;		/* Jumbo frame enable */
	unsigned int coalesce:1;	/* Rx coalescing enable */
	unsigned int tx_flow:1;		/* Tx flow control enable */
	unsigned int rx_flow:1;		/* Rx flow control enable */
	unsigned int phy_media:1;	/* 1: fiber, 0: copper */
	unsigned int link_status:1;	/* Current link status */
	unsigned char pci_rev_id;	/* PCI revision ID */
	struct netdev_desc *last_tx;	/* Last Tx descriptor used. */
	unsigned long cur_rx, old_rx;	/* Producer/consumer ring indices */
	unsigned long cur_tx, old_tx;
	struct timer_list timer;
	int wake_polarity;
	char name[256];		/* net device description */
	u8 duplex_polarity;
	u16 mcast_filter[4];
	u16 advertising;	/* NWay media advertisement */
	u16 negotiate;		/* Negotiated media */
	int phy_addr;		/* PHY addresses. */
};

/* The station address location in the EEPROM. */
#ifdef MEM_MAPPING
#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
#else
#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO  | PCI_ADDR0)
#endif
/* The struct pci_device_id consist of:
        vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
        subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
        class                   Device class to match. The class_mask tells which bits
        class_mask              of the class are honored during the comparison.
        driver_data             Data private to the driver.
*/
static struct pci_device_id rio_pci_tbl[] = {
	{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{0,}
};
MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
#define TX_TIMEOUT  (4*HZ)
#define PACKET_SIZE		1536
#define MAX_JUMBO		8000
#define RIO_IO_SIZE             340
#define DEFAULT_RXC		5
#define DEFAULT_RXT		750
#define DEFAULT_TXC		1
#define MAX_TXC			8
#endif				/* __DL2K_H__ */