dl2k.h

Linux Kernel 2.6.9 for OMAP1710

/*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
/*  
    Copyright (c) 2001, 2002 by D-Link Corporation
    Written by Edward Peng.<[e-mail]>
    Created 03-May-2001, base on Linux' sundance.c.

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
*/

#ifndef __DL2K_H__
#define __DL2K_H__

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/crc32.h>
#include <linux/ethtool.h>
#include <asm/processor.h>	/* Processor type for cache alignment. */
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/time.h>
#define TX_RING_SIZE	256
#define TX_QUEUE_LEN	(TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
#define RX_RING_SIZE 	256
#define TX_TOTAL_SIZE	TX_RING_SIZE*sizeof(struct netdev_desc)
#define RX_TOTAL_SIZE	RX_RING_SIZE*sizeof(struct netdev_desc)

/* This driver was written to use PCI memory space, however x86-oriented
   hardware often uses I/O space accesses. */
#ifndef MEM_MAPPING
#undef readb
#undef readw
#undef readl
#undef writeb
#undef writew
#undef writel
#define readb inb
#define readw inw
#define readl inl
#define writeb outb
#define writew outw
#define writel outl
#endif

/* Offsets to the device registers.
   Unlike software-only systems, device drivers interact with complex hardware.
   It's not useful to define symbolic names for every register bit in the
   device.  The name can only partially document the semantics and make
   the driver longer and more difficult to read.
   In general, only the important configuration values or bits changed
   multiple times should be defined symbolically.
*/
enum dl2x_offsets {
	/* I/O register offsets */
	DMACtrl = 0x00,
	RxDMAStatus = 0x08,
	TFDListPtr0 = 0x10,
	TFDListPtr1 = 0x14,
	TxDMABurstThresh = 0x18,
	TxDMAUrgentThresh = 0x19,
	TxDMAPollPeriod = 0x1a,
	RFDListPtr0 = 0x1c,
	RFDListPtr1 = 0x20,
	RxDMABurstThresh = 0x24,
	RxDMAUrgentThresh = 0x25,
	RxDMAPollPeriod = 0x26,
	RxDMAIntCtrl = 0x28,
	DebugCtrl = 0x2c,
	ASICCtrl = 0x30,
	FifoCtrl = 0x38,
	RxEarlyThresh = 0x3a,
	FlowOffThresh = 0x3c,
	FlowOnThresh = 0x3e,
	TxStartThresh = 0x44,
	EepromData = 0x48,
	EepromCtrl = 0x4a,
	ExpromAddr = 0x4c,
	Exprodata = 0x50,
	WakeEvent = 0x51,
	CountDown = 0x54,
	IntStatusAck = 0x5a,
	IntEnable = 0x5c,
	IntStatus = 0x5e,
	TxStatus = 0x60,
	MACCtrl = 0x6c,
	VLANTag = 0x70,
	PhyCtrl = 0x76,
	StationAddr0 = 0x78,
	StationAddr1 = 0x7a,
	StationAddr2 = 0x7c,
	VLANId = 0x80,
	MaxFrameSize = 0x86,
	ReceiveMode = 0x88,
	HashTable0 = 0x8c,
	HashTable1 = 0x90,
	RmonStatMask = 0x98,
	StatMask = 0x9c,
	RxJumboFrames = 0xbc,
	TCPCheckSumErrors = 0xc0,
	IPCheckSumErrors = 0xc2,
	UDPCheckSumErrors = 0xc4,
	TxJumboFrames = 0xf4,
	/* Ethernet MIB statistic register offsets */
	OctetRcvOk = 0xa8,
	McstOctetRcvOk = 0xac,
	BcstOctetRcvOk = 0xb0,
	FramesRcvOk = 0xb4,
	McstFramesRcvdOk = 0xb8,
	BcstFramesRcvdOk = 0xbe,
	MacControlFramesRcvd = 0xc6,
	FrameTooLongErrors = 0xc8,
	InRangeLengthErrors = 0xca,
	FramesCheckSeqErrors = 0xcc,
	FramesLostRxErrors = 0xce,
	OctetXmtOk = 0xd0,
	McstOctetXmtOk = 0xd4,
	BcstOctetXmtOk = 0xd8,
	FramesXmtOk = 0xdc,
	McstFramesXmtdOk = 0xe0,
	FramesWDeferredXmt = 0xe4,
	LateCollisions = 0xe8,
	MultiColFrames = 0xec,
	SingleColFrames = 0xf0,
	BcstFramesXmtdOk = 0xf6,
	CarrierSenseErrors = 0xf8,
	MacControlFramesXmtd = 0xfa,
	FramesAbortXSColls = 0xfc,
	FramesWEXDeferal = 0xfe,
	/* RMON statistic register offsets */
	EtherStatsCollisions = 0x100,
	EtherStatsOctetsTransmit = 0x104,
	EtherStatsPktsTransmit = 0x108,
	EtherStatsPkts64OctetTransmit = 0x10c,
	EtherStats65to127OctetsTransmit = 0x110,
	EtherStatsPkts128to255OctetsTransmit = 0x114,
	EtherStatsPkts256to511OctetsTransmit = 0x118,
	EtherStatsPkts512to1023OctetsTransmit = 0x11c,
	EtherStatsPkts1024to1518OctetsTransmit = 0x120,
	EtherStatsCRCAlignErrors = 0x124,
	EtherStatsUndersizePkts = 0x128,
	EtherStatsFragments = 0x12c,
	EtherStatsJabbers = 0x130,
	EtherStatsOctets = 0x134,
	EtherStatsPkts = 0x138,
	EtherStats64Octets = 0x13c,
	EtherStatsPkts65to127Octets = 0x140,
	EtherStatsPkts128to255Octets = 0x144,
	EtherStatsPkts256to511Octets = 0x148,
	EtherStatsPkts512to1023Octets = 0x14c,
	EtherStatsPkts1024to1518Octets = 0x150,
};

/* Bits in the interrupt status/mask registers. */
enum IntStatus_bits {
	InterruptStatus = 0x0001,
	HostError = 0x0002,
	MACCtrlFrame = 0x0008,
	TxComplete = 0x0004,
	RxComplete = 0x0010,
	RxEarly = 0x0020,
	IntRequested = 0x0040,
	UpdateStats = 0x0080,
	LinkEvent = 0x0100,
	TxDMAComplete = 0x0200,
	RxDMAComplete = 0x0400,
	RFDListEnd = 0x0800,
	RxDMAPriority = 0x1000,
};

/* Bits in the ReceiveMode register. */
enum ReceiveMode_bits {
	ReceiveUnicast = 0x0001,
	ReceiveMulticast = 0x0002,
	ReceiveBroadcast = 0x0004,
	ReceiveAllFrames = 0x0008,
	ReceiveMulticastHash = 0x0010,
	ReceiveIPMulticast = 0x0020,
	ReceiveVLANMatch = 0x0100,
	ReceiveVLANHash = 0x0200,
};
/* Bits in MACCtrl. */
enum MACCtrl_bits {
	DuplexSelect = 0x20,
	TxFlowControlEnable = 0x80,
	RxFlowControlEnable = 0x0100,
	RcvFCS = 0x200,
	AutoVLANtagging = 0x1000,
	AutoVLANuntagging = 0x2000,
	StatsEnable = 0x00200000,
	StatsDisable = 0x00400000,
	StatsEnabled = 0x00800000,
	TxEnable = 0x01000000,
	TxDisable = 0x02000000,
	TxEnabled = 0x04000000,
	RxEnable = 0x08000000,
	RxDisable = 0x10000000,
	RxEnabled = 0x20000000,
};

enum ASICCtrl_LoWord_bits {
	PhyMedia = 0x0080,
};
	
enum ASICCtrl_HiWord_bits {
	GlobalReset = 0x0001,
	RxReset = 0x0002,
	TxReset = 0x0004,
	DMAReset = 0x0008,
	FIFOReset = 0x0010,
	NetworkReset = 0x0020,
	HostReset = 0x0040,
	ResetBusy = 0x0400,
};

/* Transmit Frame Control bits */
enum TFC_bits {
	DwordAlign = 0x00000000,
	WordAlignDisable = 0x00030000,
	WordAlign = 0x00020000,
	TCPChecksumEnable = 0x00040000,
	UDPChecksumEnable = 0x00080000,
	IPChecksumEnable = 0x00100000,
	FCSAppendDisable = 0x00200000,
	TxIndicate = 0x00400000,
	TxDMAIndicate = 0x00800000,
	FragCountShift = 24,
	VLANTagInsert = 0x0000000010000000,
	TFDDone = 0x80000000,
	VIDShift = 32,
	UsePriorityShift = 48,
};

/* Receive Frames Status bits */
enum RFS_bits {
	RxFIFOOverrun = 0x00010000,
	RxRuntFrame = 0x00020000,
	RxAlignmentError = 0x00040000,
	RxFCSError = 0x00080000,
	RxOverSizedFrame = 0x00100000,
	RxLengthError = 0x00200000,
	VLANDetected = 0x00400000,
	TCPDetected = 0x00800000,
	TCPError = 0x01000000,
	UDPDetected = 0x02000000,
	UDPError = 0x04000000,
	IPDetected = 0x08000000,
	IPError = 0x10000000,
	FrameStart = 0x20000000,
	FrameEnd = 0x40000000,
	RFDDone = 0x80000000,
	TCIShift = 32,
	RFS_Errors = 0x003f0000,
};

#define MII_RESET_TIME_OUT		10000
/* MII register */
enum _mii_reg {
	MII_BMCR = 0,
	MII_BMSR = 1,
	MII_PHY_ID1 = 2,
	MII_PHY_ID2 = 3,
	MII_ANAR = 4,
	MII_ANLPAR = 5,
	MII_ANER = 6,
	MII_ANNPT = 7,
	MII_ANLPRNP = 8,
	MII_MSCR = 9,
	MII_MSSR = 10,
	MII_ESR = 15,
	MII_PHY_SCR = 16,
};
/* PCS register */
enum _pcs_reg {
	PCS_BMCR = 0,
	PCS_BMSR = 1,
	PCS_ANAR = 4,
	PCS_ANLPAR = 5,
	PCS_ANER = 6,
	PCS_ANNPT = 7,
	PCS_ANLPRNP = 8,
	PCS_ESR = 15,
};

/* Basic Mode Control Register */
typedef union t_MII_BMCR {
	u16 image;
	struct {
		u16 _bit_5_0:6;	// bit 5:0
		u16 speed1000:1;	// bit 6
		u16 col_test_enable:1;	// bit 7
		u16 duplex_mode:1;	// bit 8
		u16 restart_an:1;	// bit 9
		u16 isolate:1;	// bit 10
		u16 power_down:1;	// bit 11
		u16 an_enable:1;	// bit 12
		u16 speed100:1;	// bit 13
		u16 loopback:1;	// bit 14
		u16 reset:1;	// bit 15
	} bits;
} BMCR_t, *PBMCR_t;

enum _mii_bmcr {
	MII_BMCR_RESET = 0x8000,
	MII_BMCR_LOOP_BACK = 0x4000,
	MII_BMCR_SPEED_LSB = 0x2000,
	MII_BMCR_AN_ENABLE = 0x1000,
	MII_BMCR_POWER_DOWN = 0x0800,
	MII_BMCR_ISOLATE = 0x0400,
	MII_BMCR_RESTART_AN = 0x0200,
	MII_BMCR_DUPLEX_MODE = 0x0100,
	MII_BMCR_COL_TEST = 0x0080,
	MII_BMCR_SPEED_MSB = 0x0040,
	MII_BMCR_SPEED_RESERVED = 0x003f,
	MII_BMCR_SPEED_10 = 0,
	MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
	MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
};

/* Basic Mode Status Register */
typedef union t_MII_BMSR {
	u16 image;
	struct {
		u16 ext_capability:1;	// bit 0
		u16 japper_detect:1;	// bit 1
		u16 link_status:1;	// bit 2
		u16 an_ability:1;	// bit 3
		u16 remote_fault:1;	// bit 4
		u16 an_complete:1;	// bit 5
		u16 preamble_supp:1;	// bit 6
		u16 _bit_7:1;	// bit 7
		u16 ext_status:1;	// bit 8
		u16 media_100BT2_HD:1;	// bit 9
		u16 media_100BT2_FD:1;	// bit 10
		u16 media_10BT_HD:1;	// bit 11
		u16 media_10BT_FD:1;	// bit 12
		u16 media_100BX_HD:1;	// bit 13
		u16 media_100BX_FD:1;	// bit 14
		u16 media_100BT4:1;	// bit 15
	} bits;
} BMSR_t, *PBMSR_t;