macmace.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 711 行 · 第 1/2 页

	psc_write_word(PSC_ENETWR_CTL, 0x9000);
	psc_write_word(PSC_ENETRD_CTL, 0x9000);
	psc_write_word(PSC_ENETWR_CTL, 0x0400);
	psc_write_word(PSC_ENETRD_CTL, 0x0400);

#if 0
	/* load up the hardware address */
	
	mb->iac = ADDRCHG | PHYADDR;
	
	while ((mb->iac & ADDRCHG) != 0);
	
	for (i = 0; i < 6; ++i)
		mb->padr = dev->dev_addr[i];

	/* clear the multicast filter */
	mb->iac = ADDRCHG | LOGADDR;

	while ((mb->iac & ADDRCHG) != 0);
	
	for (i = 0; i < 8; ++i)
		mb->ladrf = 0;

	mb->plscc = PORTSEL_GPSI + ENPLSIO;

	mb->maccc = ENXMT | ENRCV;
	mb->imr = RCVINT;
#endif

	mace_rxdma_reset(dev);
	mace_txdma_reset(dev);
	
	return 0;
}

/*
 * Shut down the mace and its interrupt channel
 */
 
static int mace_close(struct net_device *dev)
{
	struct mace_data *mp = (struct mace_data *) dev->priv;
	volatile struct mace *mb = mp->mace;

	mb->maccc = 0;		/* disable rx and tx	 */
	mb->imr = 0xFF;		/* disable all irqs	 */
	mace_dma_off(dev);	/* disable rx and tx dma */

	free_irq(dev->irq, dev);
	free_irq(IRQ_MAC_MACE_DMA, dev);

	free_pages((u32) mp->rx_ring, N_RX_PAGES);
	free_pages((u32) mp->tx_ring, 0);

	return 0;
}

/*
 * Transmit a frame
 */
 
static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
{
	struct mace_data *mp = (struct mace_data *) dev->priv;

	/* Stop the queue if the buffer is full */

	if (!mp->tx_count) {
		netif_stop_queue(dev);
		return 1;
	}
	mp->tx_count--;
	
	mp->stats.tx_packets++;
	mp->stats.tx_bytes += skb->len;

	/* We need to copy into our xmit buffer to take care of alignment and caching issues */

	memcpy((void *) mp->tx_ring, skb->data, skb->len);

	/* load the Tx DMA and fire it off */

	psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32)  mp->tx_ring_phys);
	psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
	psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);

	mp->tx_slot ^= 0x10;

	dev_kfree_skb(skb);

	return 0;
}

static struct net_device_stats *mace_stats(struct net_device *dev)
{
	struct mace_data *p = (struct mace_data *) dev->priv;
	return &p->stats;
}

static void mace_set_multicast(struct net_device *dev)
{
	struct mace_data *mp = (struct mace_data *) dev->priv;
	volatile struct mace *mb = mp->mace;
	int i, j;
	u32 crc;
	u8 maccc;

	maccc = mb->maccc;
	mb->maccc &= ~PROM;

	if (dev->flags & IFF_PROMISC) {
		mb->maccc |= PROM;
	} else {
		unsigned char multicast_filter[8];
		struct dev_mc_list *dmi = dev->mc_list;

		if (dev->flags & IFF_ALLMULTI) {
			for (i = 0; i < 8; i++) {
				multicast_filter[i] = 0xFF;
			}
		} else {
			for (i = 0; i < 8; i++)
				multicast_filter[i] = 0;
			for (i = 0; i < dev->mc_count; i++) {
				crc = ether_crc_le(6, dmi->dmi_addr);
				j = crc >> 26;	/* bit number in multicast_filter */
				multicast_filter[j >> 3] |= 1 << (j & 7);
				dmi = dmi->next;
			}
		}

		mb->iac = ADDRCHG | LOGADDR;
		while (mb->iac & ADDRCHG);
		
		for (i = 0; i < 8; ++i) {
			mb->ladrf = multicast_filter[i];
		}
	}

	mb->maccc = maccc;
}

/*
 * Miscellaneous interrupts are handled here. We may end up 
 * having to bash the chip on the head for bad errors
 */
 
static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
{
	volatile struct mace *mb = mp->mace;
	static int mace_babbles, mace_jabbers;

	if (intr & MPCO) {
		mp->stats.rx_missed_errors += 256;
	}
	mp->stats.rx_missed_errors += mb->mpc;	/* reading clears it */

	if (intr & RNTPCO) {
		mp->stats.rx_length_errors += 256;
	}
	mp->stats.rx_length_errors += mb->rntpc;	/* reading clears it */

	if (intr & CERR) {
		++mp->stats.tx_heartbeat_errors;
	}
	if (intr & BABBLE) {
		if (mace_babbles++ < 4) {
			printk(KERN_DEBUG "mace: babbling transmitter\n");
		}
	}
	if (intr & JABBER) {
		if (mace_jabbers++ < 4) {
			printk(KERN_DEBUG "mace: jabbering transceiver\n");
		}
	}
}

/*
 *	A transmit error has occurred. (We kick the transmit side from
 *	the DMA completion)
 */
 
static void mace_xmit_error(struct net_device *dev)
{
	struct mace_data *mp = (struct mace_data *) dev->priv;
	volatile struct mace *mb = mp->mace;
	u8 xmtfs, xmtrc;
	
	xmtfs = mb->xmtfs;
	xmtrc = mb->xmtrc;
	
	if (xmtfs & XMTSV) {
		if (xmtfs & UFLO) {
			printk("%s: DMA underrun.\n", dev->name);
			mp->stats.tx_errors++;
			mp->stats.tx_fifo_errors++;
			mace_txdma_reset(dev);
		}
		if (xmtfs & RTRY) {
			mp->stats.collisions++;
		}
	}			
}

/*
 *	A receive interrupt occurred.
 */
 
static void mace_recv_interrupt(struct net_device *dev)
{
/*	struct mace_data *mp = (struct mace_data *) dev->priv; */
//	volatile struct mace *mb = mp->mace;
}

/*
 * Process the chip interrupt
 */
 
static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	struct net_device *dev = (struct net_device *) dev_id;
	struct mace_data *mp = (struct mace_data *) dev->priv;
	volatile struct mace *mb = mp->mace;
	u8 ir;
	
	ir = mb->ir;
	mace_handle_misc_intrs(mp, ir);
	
	if (ir & XMTINT) {
		mace_xmit_error(dev);
	}
	if (ir & RCVINT) {
		mace_recv_interrupt(dev);
	}
	return IRQ_HANDLED;
}

static void mace_tx_timeout(struct net_device *dev)
{
/*	struct mace_data *mp = (struct mace_data *) dev->priv; */
//	volatile struct mace *mb = mp->mace;
}

/*
 * Handle a newly arrived frame
 */
 
static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
{
	struct mace_data *mp = (struct mace_data *) dev->priv;
	struct sk_buff *skb;

	if (mf->status & RS_OFLO) {
		printk("%s: fifo overflow.\n", dev->name);
		mp->stats.rx_errors++;
		mp->stats.rx_fifo_errors++;
	}
	if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
		mp->stats.rx_errors++;
		
	if (mf->status&RS_CLSN) {
		mp->stats.collisions++;
	}
	if (mf->status&RS_FRAMERR) {
		mp->stats.rx_frame_errors++;
	}
	if (mf->status&RS_FCSERR) {
		mp->stats.rx_crc_errors++;
	}
		
	skb = dev_alloc_skb(mf->len+2);
	if (!skb) {
		mp->stats.rx_dropped++;
		return;
	}
	skb_reserve(skb,2);
	memcpy(skb_put(skb, mf->len), mf->data, mf->len);
	
	skb->dev = dev;
	skb->protocol = eth_type_trans(skb, dev);
	netif_rx(skb);
	dev->last_rx = jiffies;
	mp->stats.rx_packets++;
	mp->stats.rx_bytes += mf->len;
}

/*
 * The PSC has passed us a DMA interrupt event.
 */
 
static irqreturn_t mace_dma_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct net_device *dev = (struct net_device *) dev_id;
	struct mace_data *mp = (struct mace_data *) dev->priv;
	int left, head;
	u16 status;
	u32 baka;

	/* Not sure what this does */

	while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
	if (!(baka & 0x60000000)) return IRQ_NONE;

	/*
	 * Process the read queue
	 */
		 
	status = psc_read_word(PSC_ENETRD_CTL);
		
	if (status & 0x2000) {
		mace_rxdma_reset(dev);
	} else if (status & 0x0100) {
		psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);

		left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
		head = N_RX_RING - left;

		/* Loop through the ring buffer and process new packages */

		while (mp->rx_tail < head) {
			mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800)));
			mp->rx_tail++;
		}
			
		/* If we're out of buffers in this ring then switch to */
		/* the other set, otherwise just reactivate this one.  */

		if (!left) {
			mace_load_rxdma_base(dev, mp->rx_slot);
			mp->rx_slot ^= 0x10;
		} else {
			psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
		}
	}
		
	/*
	 * Process the write queue
	 */

	status = psc_read_word(PSC_ENETWR_CTL);

	if (status & 0x2000) {
		mace_txdma_reset(dev);
	} else if (status & 0x0100) {
		psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
		mp->tx_sloti ^= 0x10;
		mp->tx_count++;
		netif_wake_queue(dev);
	}
	return IRQ_HANDLED;
}

MODULE_LICENSE("GPL");