omap-mcbsp.h

Linux Kernel 2.6.9 for OMAP1710

/*
 * File: omap-mcbsp.h
 *
 * Defines for Multi-Channel Buffered Serial Port
 *
 * Copyright (C) 2002 RidgeRun, Inc.
 * Author: Steve Johnson
 *
 *  This program is free software; you can redistribute	 it and/or modify it
 *  under  the terms of	 the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the	License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS	PROVIDED  ``AS	IS''  AND   ANY	 EXPRESS  OR IMPLIED
 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT,  INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *  History
 *  -------
 *  2004/08/12 Nishanth Menon Modified to integrate Audio requirements on 1610,1710
 *                            and 2420 platforms.
 */

#ifndef __OMAP_MCBSP_H
#define __OMAP_MCBSP_H

#include <asm/arch/hardware.h>

/*************************** Base Address definitions *******************************/

/* Define this for enabling the direct mcbsp read/write functions */
#define MCBSP_DIRECT_RW

/* Physical Address */
#define OMAP1610_MCBSP1_BASE_PHY 0xE1011800
#define OMAP1610_MCBSP2_BASE_PHY 0xE1011000
#define OMAP1610_MCBSP3_BASE_PHY 0xE1017000

#define OMAP1710_MCBSP1_BASE_PHY 0xE1011800
#define OMAP1710_MCBSP2_BASE_PHY 0xE1011000

#define OMAP1710_MCBSP3_BASE_PHY 0xE1017000
#define OMAP2420_MCBSP1_BASE_PHY 0x48074000
#define OMAP2420_MCBSP2_BASE_PHY 0x48076000

/* Virtual address base */
#define OMAP1610_MCBSP1_BASE     OMAP1610_MCBSP1_BASE_PHY
#define OMAP1610_MCBSP2_BASE     OMAP1610_MCBSP2_BASE_PHY
#define OMAP1610_MCBSP3_BASE     OMAP1610_MCBSP3_BASE_PHY

#define OMAP1710_MCBSP1_BASE     OMAP1710_MCBSP1_BASE_PHY
#define OMAP1710_MCBSP2_BASE     OMAP1710_MCBSP2_BASE_PHY
#define OMAP1710_MCBSP3_BASE     OMAP1710_MCBSP3_BASE_PHY

#define OMAP2420_MCBSP1_BASE     IO_ADDRESS(OMAP2420_MCBSP1_BASE_PHY)
#define OMAP2420_MCBSP2_BASE     IO_ADDRESS(OMAP2420_MCBSP2_BASE_PHY)

/*************************** Offset Definitions *******************************/

#ifdef CONFIG_ARCH_OMAP16XX
/* 1610, 1710 */
#define OMAP_MCBSP_REG_DRR2     0x00
#define OMAP_MCBSP_REG_DRR1     0x02
#define OMAP_MCBSP_REG_DXR2     0x04
#define OMAP_MCBSP_REG_DXR1     0x06
#define OMAP_MCBSP_REG_SPCR2    0x08
#define OMAP_MCBSP_REG_SPCR1    0x0A
#define OMAP_MCBSP_REG_RCR2     0x0C
#define OMAP_MCBSP_REG_RCR1     0x0E
#define OMAP_MCBSP_REG_XCR2     0x10
#define OMAP_MCBSP_REG_XCR1     0x12
#define OMAP_MCBSP_REG_SRGR2    0x14
#define OMAP_MCBSP_REG_SRGR1    0x16
#define OMAP_MCBSP_REG_MCR2     0x18
#define OMAP_MCBSP_REG_MCR1     0x1A
#define OMAP_MCBSP_REG_RCERA    0x1C
#define OMAP_MCBSP_REG_RCERB    0x1E
#define OMAP_MCBSP_REG_XCERA    0x20
#define OMAP_MCBSP_REG_XCERB    0x22
#define OMAP_MCBSP_REG_PCR      0x24
#define OMAP_MCBSP_REG_RCERC    0x26
#define OMAP_MCBSP_REG_RCERD    0x28
#define OMAP_MCBSP_REG_XCERC    0x2A
#define OMAP_MCBSP_REG_XCERD    0x2C
#define OMAP_MCBSP_REG_RCERE    0x2E
#define OMAP_MCBSP_REG_RCERF    0x30
#define OMAP_MCBSP_REG_XCERE    0x32
#define OMAP_MCBSP_REG_XCERF    0x34
#define OMAP_MCBSP_REG_RCERG    0x36
#define OMAP_MCBSP_REG_RCERH    0x38
#define OMAP_MCBSP_REG_XCERG    0x3A
#define OMAP_MCBSP_REG_XCERH    0x3C

#define OMAP_MAX_MCBSP_COUNT    3

#elif CONFIG_ARCH_OMAP24XX

/* 2420 definitions */
#define OMAP_MCBSP_REG_DRR2     0x00
#define OMAP_MCBSP_REG_DRR1     0x04
#define OMAP_MCBSP_REG_DXR2     0x08
#define OMAP_MCBSP_REG_DXR1     0x0C
#define OMAP_MCBSP_REG_SPCR2    0x10
#define OMAP_MCBSP_REG_SPCR1    0x14
#define OMAP_MCBSP_REG_RCR2     0x18
#define OMAP_MCBSP_REG_RCR1     0x1C
#define OMAP_MCBSP_REG_XCR2     0x20
#define OMAP_MCBSP_REG_XCR1     0x24
#define OMAP_MCBSP_REG_SRGR2    0x28
#define OMAP_MCBSP_REG_SRGR1    0x2C
#define OMAP_MCBSP_REG_MCR2     0x30
#define OMAP_MCBSP_REG_MCR1     0x34
#define OMAP_MCBSP_REG_RCERA    0x38
#define OMAP_MCBSP_REG_RCERB    0x3C
#define OMAP_MCBSP_REG_XCERA    0x40
#define OMAP_MCBSP_REG_XCERB    0x44
#define OMAP_MCBSP_REG_PCR      0x48

#define OMAP_MAX_MCBSP_COUNT    2
/* DMA Trigger values */
#define MCBSP1_DMA_TX           30
#define MCBSP1_DMA_RX           31
#define MCBSP2_DMA_TX           33
#define MCBSP2_DMA_RX           34

#define AUDIO_MCBSP_DATAWRITE   (OMAP2420_MCBSP2_BASE_PHY+OMAP_MCBSP_REG_DXR1)
#define AUDIO_MCBSP_DATAREAD    (OMAP2420_MCBSP2_BASE_PHY+OMAP_MCBSP_REG_DRR1)

#define AUDIO_DMA_TX            MCBSP2_DMA_TX
#define AUDIO_DMA_RX            MCBSP2_DMA_RX

#else

#error "Not Supported configuration "

#endif				/* Offset Definitions */

/* Default clock for H4/H3/H2 */
#define DEFAULT_MCBSP_CLOCK      96000000

#define OMAP_MCBSP_READ(base, reg)	        (__raw_readw((base) + OMAP_MCBSP_REG_##reg))
#define OMAP_MCBSP_WRITE(base, reg, val)	(__raw_writew((val), (base) + OMAP_MCBSP_REG_##reg))

/*************************** Field Definitions *******************************/

#define MCBSP_BIT(ARG)      ((0x01)<<(ARG))

/* Field masks for Register SPCR1 */
#define SPCR1_DLB          MCBSP_BIT(15)
#define SPCR1_RJUST(ARG)   (((ARG) & 0x03) << 13)
#define SPCR1_CLKSTP(ARG)  (((ARG) & 0x03) << 11)
#define SPCR1_DXENA        MCBSP_BIT(7)
#define SPCR1_RINTM(ARG)   (((ARG) & 0x03) << 4)
#define SPCR1_RSYNCERR     MCBSP_BIT(3)
#define SPCR1_RFULL        MCBSP_BIT(2)
#define SPCR1_RRDY         MCBSP_BIT(1)
#define SPCR1_RRST         (0x01)

/* Field masks for Register SPCR2 */
#define SPCR2_FREE         MCBSP_BIT(9)
#define SPCR2_SOFT         MCBSP_BIT(8)
#define SPCR2_FRST         MCBSP_BIT(7)
#define SPCR2_GRST         MCBSP_BIT(6)
#define SPCR2_XINTM(ARG)   (((ARG) & 0x03) << 4)
#define SPCR2_XSYNCERR     MCBSP_BIT(3)
#define SPCR2_XEMPTY       MCBSP_BIT(2)
#define SPCR2_XRDY         MCBSP_BIT(1)
#define SPCR2_XRST         (0x01)

/* Field masks for Register RCR1 */
#define RCR1_RFRLEN1(ARG)  (((ARG) & 0x7F) << 8)
#define RCR1_RWDLEN1(ARG)  (((ARG) & 0x07) << 5)

/* Field masks for Register RCR2 */
#define RCR2_RPHASE        MCBSP_BIT(15)
#define RCR2_RFRLEN2(ARG)  (((ARG) & 0x7F) << 8)
#define RCR2_RWDLEN2(ARG)  (((ARG) & 0x07) << 5)
#define RCR2_RCOMPAND(ARG) (((ARG) & 0x03) << 3)
#define RCR2_RFIG          MCBSP_BIT(2)
#define RCR2_RDATDLY(ARG)  ((ARG) & 0x03)

/* Field masks for Register XCR1 */
#define XCR1_XFRLEN1(ARG)  (((ARG) & 0x7F) << 8)
#define XCR1_XWDLEN1(ARG)  (((ARG) & 0x07) << 5)

/* Field masks for Register XCR2 */
#define XCR2_XPHASE        MCBSP_BIT(15)
#define XCR2_XFRLEN2(ARG)  (((ARG) & 0x7F) << 8)
#define XCR2_XWDLEN2(ARG)  (((ARG) & 0x07) << 5)
#define XCR2_XCOMPAND(ARG) (((ARG) & 0x03) << 3)
#define XCR2_XFIG          MCBSP_BIT(2)
#define XCR2_XDATDLY(ARG)  ((ARG) & 0x03)

/* Field masks for Register SRGR1 */
#define SRGR1_FWID(ARG)    (((ARG) & 0xFF) << 8)
#define SRGR1_CLKGDV(ARG)  ((ARG) & 0xFF)

/* Field masks for Register SRGR2 */
#define SRGR2_GSYNC        MCBSP_BIT(15)
#define SRGR2_CLKSP        MCBSP_BIT(14)
#define SRGR2_CLKSM        MCBSP_BIT(13)
#define SRGR2_FSGM         MCBSP_BIT(12)
#define SRGR2_FPER(ARG)    ((ARG) & 0xFFF)

/* Field masks for Register MCR1 */

#define MCR1_RMCME         MCBSP_BIT(9)
#define MCR1_RPBBLK(ARG)   (((ARG) & 0x03) << 7)
#define MCR1_RPABLK(ARG)   (((ARG) & 0x03) << 5)
#define MCR1_RCBLK(ARG)    (((ARG) & 0x07) << 2)
#define MCR1_RMCM          (0x01)

/* Field masks for Register MCR2 */
#define MCR2_XMCME         MCBSP_BIT(9)
#define MCR2_XPBBLK(ARG)   (((ARG) & 0x03) << 7)
#define MCR2_XPABLK(ARG)   (((ARG) & 0x03) << 5)
#define MCR2_XCBLK(ARG)    (((ARG) & 0x07) << 2)
#define MCR2_XMCM(ARG)     ((ARG) & 0x03)

/* Field masks for Register PCR */
#define PCR_IDLEEN         MCBSP_BIT(14)
#define PCR_XIOEN          MCBSP_BIT(13)
#define PCR_RIOEN          MCBSP_BIT(12)
#define PCR_FSXM           MCBSP_BIT(11)
#define PCR_FSRM           MCBSP_BIT(10)
#define PCR_CLKXM          MCBSP_BIT(9)
#define PCR_CLKRM          MCBSP_BIT(8)
#define PCR_SCLKME         MCBSP_BIT(7)
#define PCR_CLKSSTAT       MCBSP_BIT(6)
#define PCR_DXSTAT         MCBSP_BIT(5)
#define PCR_DRSTAT         MCBSP_BIT(4)
#define PCR_FSXP           MCBSP_BIT(3)
#define PCR_FSRP           MCBSP_BIT(2)
#define PCR_CLKXP          MCBSP_BIT(1)
#define PCR_CLKRP          (0x01)

/*************************** Data Structures *******************************/

/* we don't do multichannel for now */
struct omap_mcbsp_reg_cfg {
	u16 spcr2;
	u16 spcr1;
	u16 rcr2;
	u16 rcr1;
	u16 xcr2;
	u16 xcr1;
	u16 srgr2;
	u16 srgr1;
	u16 mcr2;
	u16 mcr1;
	u16 pcr;
	u16 rcerc;
	u16 rcerd;
	u16 xcerc;
	u16 xcerd;
	u16 rcere;
	u16 rcerf;
	u16 xcere;
	u16 xcerf;
	u16 rcerg;
	u16 rcerh;
	u16 xcerg;
	u16 xcerh;
};

typedef enum {
	OMAP_MCBSP1 = 0,
	OMAP_MCBSP2,
	OMAP_MCBSP3,
} omap_mcbsp_id;

typedef enum {
	OMAP_MCBSP_WORD_8 = 0,
	OMAP_MCBSP_WORD_12,
	OMAP_MCBSP_WORD_16,
	OMAP_MCBSP_WORD_20,
	OMAP_MCBSP_WORD_24,
	OMAP_MCBSP_WORD_32,
} omap_mcbsp_word_length;

typedef enum {
	OMAP_MCBSP_CLK_RISING = 0,
	OMAP_MCBSP_CLK_FALLING,
} omap_mcbsp_clk_polarity;

typedef enum {
	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
	OMAP_MCBSP_FS_ACTIVE_LOW,
} omap_mcbsp_fs_polarity;

typedef enum {
	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
	OMAP_MCBSP_CLK_STP_MODE_DELAY,
} omap_mcbsp_clk_stp_mode;

/******* SPI specific mode **********/
typedef enum {
	OMAP_MCBSP_SPI_MASTER = 0,
	OMAP_MCBSP_SPI_SLAVE,
} omap_mcbsp_spi_mode;

struct omap_mcbsp_spi_cfg {
	omap_mcbsp_spi_mode spi_mode;
	omap_mcbsp_clk_polarity rx_clock_polarity;
	omap_mcbsp_clk_polarity tx_clock_polarity;
	omap_mcbsp_fs_polarity fsx_polarity;
	u8 clk_div;
	omap_mcbsp_clk_stp_mode clk_stp_mode;
	omap_mcbsp_word_length word_length;
};

/*************************** Function prototypes *******************************/

int omap_mcbsp_begin(unsigned int id);
int omap_mcbsp_set_rate(unsigned int id, u32 sample_rate, int bits_per_sample);
int omap_mcbsp_end(unsigned int id);

#ifdef MCBSP_DIRECT_RW
int omap_mcbsp_write(unsigned int id, u16 buf);
int omap_mcbsp_read(unsigned int id, u16 * buf);
#endif

#endif				/* Header Guard */