omap-mcspi.h
来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 263 行
H
263 行
/* * BRIEF MODULE DESCRIPTION * * SPI interface driver for the OMAP24XX Platform * * Copyright 2004 Texas Instruments Inc. * Author: Suresh Reddy. * sureshr@ti.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */#ifndef OMAP24XX_SPI_H#define OMAP24XX_SPI_H/* SPI1 Register Definitions */#define OMAP24xx_SPI1_BASE 0x48098000#define OMAP24xx_SPI1_SIZE 0x00001000#define OMAP24xx_SPI2_BASE 0x4809A000#define OMAP24xx_SPI2_SIZE 0x00001000/* offsets of SPI Registers */#define MCSPI_REVISION 0x00#define MCSPI_SYSCONFIG 0x10#define MCSPI_SYSSTATUS 0x14#define MCSPI_IRQSTATUS 0x18#define MCSPI_IRQENABLE 0x1C#define MCSPI_SYST 0x24#define MCSPI_MODULCTRL 0x28#define MCSPI_CHCONF0 0x2C#define MCSPI_CHSTAT0 0x30#define MCSPI_CHCTRL0 0x34#define MCSPI_TX0 0x38#define MCSPI_RX0 0x3C#define MCSPI_CHCONF1 0x40#define MCSPI_CHSTAT1 0x44#define MCSPI_CHCTRL1 0x48#define MCSPI_TX1 0x4C#define MCSPI_RX1 0x50/* offsets of registers which are specific to SPI1 */#define MCSPI_CHCONF2 0x54#define MCSPI_CHSTAT2 0x58#define MCSPI_CHCTRL2 0x5C#define MCSPI_TX2 0x60#define MCSPI_RX2 0x64#define MCSPI_CHCONF3 0x68#define MCSPI_CHSTAT3 0x6C#define MCSPI_CHCTRL3 0x70#define MCSPI_TX3 0x74#define MCSPI_RX3 0x78/* define bitfeilds in selected registers */#define MCSPI_SYSCONFIG_FCLKON_OCPCLKOFF (1 << 8)#define MCSPI_SYSCONFIG_FCLKOFF_OCPCLKON (2 << 8)#define MCSPI_SYSCONFIG_FCLKOFF_OCPCLKOFF (3 << 8)#define MCSPI_SYSCONFIG_ENAWAKEUP_ENABLE (1 << 2)#define MCSPI_SYSCONFIG_ENAWAKEUP_DISABLE (0 << 2)#define MCSPI_SYSCONFIG_SOFTRESET_START (1 << 1)#define MCSPI_SYSSTATUS_RESET_DONE (1 << 0)#define MCSPI_IRQSTATUS_WKS_PENDING (1 << 16)#define MCSPI_IRQSTATUS_WKS_RESET (1 << 16)#define MCSPI_IRQSTATUS_RX3FULL (1 << 14)#define MCSPI_IRQSTATUS_RX3FULL_CLEAR (1 << 14)#define MCSPI_IRQSTATUS_TX3UNDERFLOW (1 << 13)#define MCSPI_IRQSTATUS_TX3UNDERFLOW_CLEAR (1 << 13)#define MCSPI_IRQSTATUS_TX3EMPTY (1 << 12)#define MCSPI_IRQSTATUS_TX3EMPTY_CLEAR (1 << 12)#define MCSPI_IRQSTATUS_RX2FULL (1 << 10)#define MCSPI_IRQSTATUS_RX2FULL_CLEAR (1 << 10)#define MCSPI_IRQSTATUS_TX2UNDERFLOW (1 << 9)#define MCSPI_IRQSTATUS_TX2UNDERFLOW_CLEAR (1 << 9)#define MCSPI_IRQSTATUS_TX2EMPTY (1 << 8)#define MCSPI_IRQSTATUS_TX2EMPTY_CLEAR (1 << 8)#define MCSPI_IRQSTATUS_RX1FULL (1 << 6)#define MCSPI_IRQSTATUS_RX1FULL_CLEAR (1 << 6)#define MCSPI_IRQSTATUS_TX1UNDERFLOW (1 << 5)#define MCSPI_IRQSTATUS_TX1UNDERFLOW_CLEAR (1 << 5)#define MCSPI_IRQSTATUS_TX1EMPTY (1 << 4)#define MCSPI_IRQSTATUS_TX1EMPTY_CLEAR (1 << 4)#define MCSPI_IRQSTATUS_RX0OVERFLOW (1 << 3)#define MCSPI_IRQSTATUS_RX0OVERFLOW_CLEAR (1 << 3)#define MCSPI_IRQSTATUS_RX0FULL (1 << 2)#define MCSPI_IRQSTATUS_RX0FULL_CLEAR (1 << 2)#define MCSPI_IRQSTATUS_TX0UNDERFLOW (1 << 1)#define MCSPI_IRQSTATUS_TX0UNDERFLOW_CLEAR (1 << 1)#define MCSPI_IRQSTATUS_TX0EMPTY (1 << 0)#define MCSPI_IRQSTATUS_TX0EMPTY_CLEAR (1 << 0)#define MCSPI_IRQENABLE_WKE_ENABLE (1 << 16)#define MCSPI_IRQENABLE_WKE_DISABLE (0 << 16)#define MCSPI_IRQENABLE_RX3FULL_ENABLE (1 << 14)#define MCSPI_IRQENABLE_RX3FULL_DISABLE (0 << 14)#define MCSPI_IRQENABLE_TX3UNDERFLOW_ENABLE (1 << 13)#define MCSPI_IRQENABLE_TX3UNDERFLOW_DISABLE (0 << 13)#define MCSPI_IRQENABLE_TX3EMPTY_ENABLE (1 << 12)#define MCSPI_IRQENABLE_TX3EMPTY_DISABLE (0 << 12)#define MCSPI_IRQENABLE_RX2FULL_ENABLE (1 << 10)#define MCSPI_IRQENABLE_RX2FULL_DISABLE (0 << 10)#define MCSPI_IRQENABLE_TX2UNDERFLOW_ENABLE (1 << 9)#define MCSPI_IRQENABLE_TX2UNDERFLOW_DISABLE (0 << 9)#define MCSPI_IRQENABLE_TX2EMPTY_ENABLE (1 << 8)#define MCSPI_IRQENABLE_TX2EMPTY_DISABLE (0 << 8)#define MCSPI_IRQENABLE_RX1FULL_ENABLE (1 << 6)#define MCSPI_IRQENABLE_RX1FULL_DISABLE (0 << 6)#define MCSPI_IRQENABLE_TX1UNDERFLOW_ENABLE (1 << 5)#define MCSPI_IRQENABLE_TX1UNDERFLOW_DISABLE (0 << 5)#define MCSPI_IRQENABLE_TX1EMPTY_ENABLE (1 << 4)#define MCSPI_IRQENABLE_TX1EMPTY_DISABLE (0 << 4)#define MCSPI_IRQENABLE_RX0OVERFLOW_ENABLE (1 << 3)#define MCSPI_IRQENABLE_RX0OVERFLOW_DISABLE (0 << 3)#define MCSPI_IRQENABLE_RX0FULL_ENABLE (1 << 2)#define MCSPI_IRQENABLE_RX0FULL_DISABLE (0 << 2)#define MCSPI_IRQENABLE_TX0UNDERFLOW_ENABLE (1 << 1)#define MCSPI_IRQENABLE_TX0UNDERFLOW_DISABLE (0 << 1)#define MCSPI_IRQENABLE_TX0EMPTY_ENABLE (1 << 0)#define MCSPI_IRQENABLE_TX0EMPTY_DISABLE (0 << 0)#define MCSPI_MODULCTRL_SYSTEST_DISABLE (0 << 3)#define MCSPI_MODULCTRL_SYSTEST_ENABLE (1 << 3)#define MCSPI_MODULCTRL_MASTER (0 << 2)#define MCSPI_MODULCTRL_SLAVE (1 << 2)#define MCSPI_MODULCTRL_LITTLEEND (0 << 1)#define MCSPI_MODULCTRL_BIGEND (1 << 1)#define MCSPI_CHCONF_SPIENSLV_CS0 (0 << 19)#define MCSPI_CHCONF_SPIENSLV_CS1 (1 << 19)#define MCSPI_CHCONF_SPIENSLV_CS2 (2 << 19)#define MCSPI_CHCONF_SPIENSLV_CS3 (3 << 19)#define MCSPI_CHCONF_IS_DL0RECEIVE (0 << 18)#define MCSPI_CHCONF_IS_DL1RECEIVE (1 << 18)#define MCSPI_CHCONF_DPE1_TRANSMIT (0 << 17)#define MCSPI_CHCONF_DPE1_NO_TRANSMIT (1 << 17)#define MCSPI_CHCONF_DPE0_TRANSMIT (0 << 16)#define MCSPI_CHCONF_DPE0_NO_TRANSMIT (1 << 16)#define MCSPI_CHCONF_DMAR_DISABLE (0 << 15)#define MCSPI_CHCONF_DMAR_ENABLE (1 << 15)#define MCSPI_CHCONF_DMAW_DISABLE (0 << 14)#define MCSPI_CHCONF_DMAW_ENABLE (1 << 14)#define MCSPI_CHCONF_TRANSRECEIVE (0 << 12)#define MCSPI_CHCONF_RECEIVEONLY (1 << 12)#define MCSPI_CHCONF_TRANSONLY (2 << 12)#define MCSPI_CHCONF_WL4 (3 << 7)#define MCSPI_CHCONF_WL5 (4 << 7)#define MCSPI_CHCONF_WL6 (5 << 7)#define MCSPI_CHCONF_WL7 (6 << 7)#define MCSPI_CHCONF_WL8 (7 << 7)#define MCSPI_CHCONF_WL9 (8 << 7)#define MCSPI_CHCONF_WL10 (9 << 7)#define MCSPI_CHCONF_WL11 (10 << 7)#define MCSPI_CHCONF_WL12 (11 << 7)#define MCSPI_CHCONF_WL13 (12 << 7)#define MCSPI_CHCONF_WL14 (13 << 7)#define MCSPI_CHCONF_WL15 (14 << 7)#define MCSPI_CHCONF_WL16 (15 << 7)#define MCSPI_CHCONF_WL17 (16 << 7)#define MCSPI_CHCONF_WL18 (17 << 7)#define MCSPI_CHCONF_WL19 (18 << 7)#define MCSPI_CHCONF_WL20 (19 << 7)#define MCSPI_CHCONF_WL21 (20 << 7)#define MCSPI_CHCONF_WL22 (21 << 7)#define MCSPI_CHCONF_WL23 (22 << 7)#define MCSPI_CHCONF_WL24 (23 << 7)#define MCSPI_CHCONF_WL25 (24 << 7)#define MCSPI_CHCONF_WL26 (25 << 7)#define MCSPI_CHCONF_WL27 (26 << 7)#define MCSPI_CHCONF_WL28 (27 << 7)#define MCSPI_CHCONF_WL29 (28 << 7)#define MCSPI_CHCONF_WL30 (29 << 7)#define MCSPI_CHCONF_WL31 (30 << 7)#define MCSPI_CHCONF_WL32 (31 << 7)#define MCSPI_CHCONF_EPOL_HIGH (0 << 6)#define MCSPI_CHCONF_EPOL_LOW (1 << 6)#define MCSPI_CHCONF_CLKD_1 (0 << 2)#define MCSPI_CHCONF_CLKD_2 (1 << 2)#define MCSPI_CHCONF_CLKD_4 (2 << 2)#define MCSPI_CHCONF_CLKD_8 (3 << 2)#define MCSPI_CHCONF_CLKD_16 (4 << 2)#define MCSPI_CHCONF_CLKD_32 (5 << 2)#define MCSPI_CHCONF_CLKD_64 (6 << 2)#define MCSPI_CHCONF_CLKD_128 (7 << 2)#define MCSPI_CHCONF_CLKD_256 (8 << 2)#define MCSPI_CHCONF_CLKD_512 (9 << 2)#define MCSPI_CHCONF_CLKD_1024 (10 << 2)#define MCSPI_CHCONF_CLKD_2048 (11 << 2)#define MCSPI_CHCONF_CLKD_4096 (12 << 2)#define MCSPI_CHCONF_CLKD_8192 (13 << 2)#define MCSPI_CHCONF_CLKD_16384 (14 << 2)#define MCSPI_CHCONF_CLKD_32768 (15 << 2)#define MCSPI_CHCONF_POL_HIGH (0 << 1)#define MCSPI_CHCONF_POL_LOW (1 << 1)#define MCSPI_CHCONF_PHA_ODD (0 << 0)#define MCSPI_CHCONF_PHA_EVEN (1 << 0)#define MCSPI_CHSTAT_TXS_FULL (0 << 1)#define MCSPI_CHSTAT_TXS_EMPTY (1 << 1)#define MCSPI_CHSTAT_RXS_EMPTY (0 << 0)#define MCSPI_CHSTAT_RXS_FULL (1 << 0)#define MCSPI_CHCTRL_ACTIVE (1 << 0)#define MCSPI_CHCTRL_NOTACTIVE (0 << 0)#define MCSPI_CHCONF 0x2C#define MCSPI_CHSTAT 0x30#define MCSPI_CHCTRL 0x34#define MCSPI_TX 0x38#define MCSPI_RX 0x3Cstruct spi_channel_config { u32 mode; /* MAster/Slave */ u32 endianess; /* Little/Big */ u32 transmitreceive; /*Receive/transmit/both */ u32 wordlength; /* Length of the word to be transmitted */ u32 spipolarity; /* Polaroty of SPIEN */ u32 clkphase; /* clock phase */ u32 clkpolarity; /* clock polaroty */ u32 clkdivisor; /* clock divisor */};#define MASTER 0#define CHANNEL_OFFSET 0x14#define TX_STARTBIT 0x00#define RX_STARTBIT 0x02#define TX_OFFSET 0x04#define RX_OFFSET 0x04#define SPI0 0/* Exported function prototypes */int omap24xx_spi1_init(void);int omap24xx_spi2_init(void);int omap24xx_spi1_exit(void);int omap24xx_spi2_exit(void);int omap24xx_spi_channelconfig(int, struct spi_channel_config *);void omap24xx_spi_enablechannel(int);void omap24xx_spi_disablechannel(int);void omap24xx_spi_writetochannel(int, u32);u32 omap24xx_spi_readfromchannel(int);u32 omap24xx_spi_readwritechannel(int, u32);#endif⌨️ 快捷键说明
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