3w-9xxx.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 705 行 · 第 1/2 页

#define TW_ESCALADE_MAX_SGL_LENGTH 41
#define TW_APACHE_CMD_PKT_SIZE 5
#else
#define TW_APACHE_MAX_SGL_LENGTH 109
#define TW_ESCALADE_MAX_SGL_LENGTH 62
#define TW_APACHE_CMD_PKT_SIZE 4
#endif
#define TW_ATA_PASS_SGL_MAX                   60
#define TW_Q_LENGTH			      256
#define TW_Q_START			      0
#define TW_MAX_SLOT			      32
#define TW_MAX_RESET_TRIES		      2
#define TW_MAX_CMDS_PER_LUN		      254
#define TW_MAX_RESPONSE_DRAIN		      256
#define TW_MAX_AEN_DRAIN		      40
#define TW_IN_IOCTL                           2
#define TW_IN_CHRDEV_IOCTL                    3
#define TW_IN_ATTENTION_LOOP		      4
#define TW_MAX_SECTORS                        256
#define TW_AEN_WAIT_TIME                      1000
#define TW_IOCTL_WAIT_TIME                    (1 * HZ) /* 1 second */
#define TW_MAX_CDB_LEN                        16
#define TW_ISR_DONT_COMPLETE                  2
#define TW_ISR_DONT_RESULT                    3
#define TW_IOCTL_CHRDEV_TIMEOUT               60 /* 60 seconds */
#define TW_IOCTL_CHRDEV_FREE                  -1
#define TW_COMMAND_OFFSET                     128 /* 128 bytes */
#define TW_VERSION_TABLE                      0x0402
#define TW_TIMEKEEP_TABLE		      0x040A
#define TW_INFORMATION_TABLE		      0x0403
#define TW_PARAM_FWVER			      3
#define TW_PARAM_FWVER_LENGTH		      16
#define TW_PARAM_BIOSVER		      4
#define TW_PARAM_BIOSVER_LENGTH		      16
#define TW_PARAM_PORTCOUNT		      3
#define TW_PARAM_PORTCOUNT_LENGTH	      1
#define TW_MIN_SGL_LENGTH                     0x200 /* 512 bytes */
#define TW_MAX_SENSE_LENGTH                   256
#define TW_EVENT_SOURCE_AEN                   0x1000
#define TW_EVENT_SOURCE_COMMAND               0x1001
#define TW_EVENT_SOURCE_PCHIP                 0x1002
#define TW_EVENT_SOURCE_DRIVER                0x1003
#define TW_IOCTL_GET_COMPATIBILITY_INFO	      0x101
#define TW_IOCTL_GET_LAST_EVENT               0x102
#define TW_IOCTL_GET_FIRST_EVENT              0x103
#define TW_IOCTL_GET_NEXT_EVENT               0x104
#define TW_IOCTL_GET_PREVIOUS_EVENT           0x105
#define TW_IOCTL_GET_LOCK                     0x106
#define TW_IOCTL_RELEASE_LOCK                 0x107
#define TW_IOCTL_FIRMWARE_PASS_THROUGH        0x108
#define TW_IOCTL_ERROR_STATUS_NOT_LOCKED      0x1001 // Not locked
#define TW_IOCTL_ERROR_STATUS_LOCKED          0x1002 // Already locked
#define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS  0x1003 // No more events
#define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER     0x1004 // AEN clobber occurred
#define TW_IOCTL_ERROR_OS_EFAULT	      -EFAULT // Bad address
#define TW_IOCTL_ERROR_OS_EINTR		      -EINTR  // Interrupted system call
#define TW_IOCTL_ERROR_OS_EINVAL	      -EINVAL // Invalid argument
#define TW_IOCTL_ERROR_OS_ENOMEM	      -ENOMEM // Out of memory
#define TW_IOCTL_ERROR_OS_ERESTARTSYS	      -ERESTARTSYS // Restart system call
#define TW_IOCTL_ERROR_OS_EIO		      -EIO // I/O error
#define TW_IOCTL_ERROR_OS_ENOTTY	      -ENOTTY // Not a typewriter
#define TW_IOCTL_ERROR_OS_ENODEV	      -ENODEV // No such device
#define TW_ALLOCATION_LENGTH		      128
#define TW_SENSE_DATA_LENGTH		      18
#define TW_STATUS_CHECK_CONDITION	      2
#define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED   0x10a
#define TW_ERROR_UNIT_OFFLINE                 0x128
#define TW_MESSAGE_SOURCE_CONTROLLER_ERROR    3
#define TW_MESSAGE_SOURCE_CONTROLLER_EVENT    4
#define TW_MESSAGE_SOURCE_LINUX_DRIVER        6
#define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER
#define TW_MESSAGE_SOURCE_LINUX_OS            9
#define TW_OS TW_MESSAGE_SOURCE_LINUX_OS
#if BITS_PER_LONG > 32
#define TW_COMMAND_SIZE			      5
#define TW_DMA_MASK			      DMA_64BIT_MASK
#else
#define TW_COMMAND_SIZE			      4
#define TW_DMA_MASK			      DMA_32BIT_MASK
#endif
#ifndef PCI_DEVICE_ID_3WARE_9000
#define PCI_DEVICE_ID_3WARE_9000 0x1002
#endif

/* Bitmask macros to eliminate bitfields */

/* opcode: 5, reserved: 3 */
#define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_OP_OUT(x) (x & 0x1f)

/* opcode: 5, sgloffset: 3 */
#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_SGL_OUT(x) ((x >> 5) & 0x7)

/* severity: 3, reserved: 5 */
#define TW_SEV_OUT(x) (x & 0x7)

/* reserved_1: 4, response_id: 8, reserved_2: 20 */
#define TW_RESID_OUT(x) ((x >> 4) & 0xff)

/* Macros */
#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
#define TW_STATUS_REG_ADDR(x) ((unsigned char *)x->base_addr + 0x4)
#if BITS_PER_LONG > 32
#define TW_COMMAND_QUEUE_REG_ADDR(x) ((unsigned char *)x->base_addr + 0x20)
#else
#define TW_COMMAND_QUEUE_REG_ADDR(x) ((unsigned char *)x->base_addr + 0x8)
#endif
#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char *)x->base_addr + 0xC)
#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
			TW_CONTROL_CLEAR_HOST_INTERRUPT | \
			TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
			TW_CONTROL_MASK_COMMAND_INTERRUPT | \
			TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
			TW_CONTROL_CLEAR_ERROR_STATUS | \
			TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_PRINTK(h,a,b,c) { \
if (h) \
printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
else \
printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
}

#pragma pack(1)

/* Scatter Gather List Entry */
typedef struct TAG_TW_SG_Entry {
	unsigned long address;
	u32 length;
} TW_SG_Entry;

/* Command Packet */
typedef struct TW_Command {
	unsigned char opcode__sgloffset;
	unsigned char size;
	unsigned char request_id;
	unsigned char unit__hostid;
	/* Second DWORD */
	unsigned char status;
	unsigned char flags;
	union {
		unsigned short block_count;
		unsigned short parameter_count;
	} byte6_offset;
	union {
		struct {
			u32 lba;
			TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
#if BITS_PER_LONG > 32
			u32 padding[2];	/* pad to 512 bytes */
#else
			u32 padding;
#endif
		} io;
		struct {
			TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
#if BITS_PER_LONG > 32
			u32 padding[3];
#else
			u32 padding[2];
#endif
		} param;
	} byte8_offset;
} TW_Command;

/* Scatter gather element for 9000+ controllers */
typedef struct TAG_TW_SG_Apache {
	unsigned long address;
	u32 length;
} TW_SG_Apache;

/* Command Packet for 9000+ controllers */
typedef struct TAG_TW_Command_Apache {
	unsigned char opcode__reserved;
	unsigned char unit;
	unsigned short request_id;
	unsigned char status;
	unsigned char sgl_offset;
	unsigned short sgl_entries;
	unsigned char cdb[16];
	TW_SG_Apache sg_list[TW_APACHE_MAX_SGL_LENGTH];
#if BITS_PER_LONG > 32
	unsigned char padding[8];
#endif
} TW_Command_Apache;

/* New command packet header */
typedef struct TAG_TW_Command_Apache_Header {
	unsigned char sense_data[TW_SENSE_DATA_LENGTH];
	struct {
		char reserved[4];
		unsigned short error;
		unsigned char padding;
		unsigned char severity__reserved;
	} status_block;
	unsigned char err_specific_desc[98];
	struct {
		unsigned char size_header;
		unsigned short reserved;
		unsigned char size_sense;
	} header_desc;
} TW_Command_Apache_Header;

/* This struct is a union of the 2 command packets */
typedef struct TAG_TW_Command_Full {
	TW_Command_Apache_Header header;
	union {
		TW_Command oldcommand;
		TW_Command_Apache newcommand;
	} command;
} TW_Command_Full;

/* Initconnection structure */
typedef struct TAG_TW_Initconnect {
	unsigned char opcode__reserved;
	unsigned char size;
	unsigned char request_id;
	unsigned char res2;
	unsigned char status;
	unsigned char flags;
	unsigned short message_credits;
	u32 features;
	unsigned short fw_srl;
	unsigned short fw_arch_id;
	unsigned short fw_branch;
	unsigned short fw_build;
	u32 result;
} TW_Initconnect;

/* Event info structure */
typedef struct TAG_TW_Event
{
	unsigned int sequence_id;
	unsigned int time_stamp_sec;
	unsigned short aen_code;
	unsigned char severity;
	unsigned char retrieved;
	unsigned char repeat_count;
	unsigned char parameter_len;
	unsigned char parameter_data[98];
} TW_Event;

typedef struct TAG_TW_Ioctl_Driver_Command {
	unsigned int control_code;
	unsigned int status;
	unsigned int unique_id;
	unsigned int sequence_id;
	unsigned int os_specific;
	unsigned int buffer_length;
} TW_Ioctl_Driver_Command;

typedef struct TAG_TW_Ioctl_Apache {
	TW_Ioctl_Driver_Command driver_command;
        char padding[488];
	TW_Command_Full firmware_command;
	char data_buffer[1];
} TW_Ioctl_Buf_Apache;

/* Lock structure for ioctl get/release lock */
typedef struct TAG_TW_Lock {
	unsigned long timeout_msec;
	unsigned long time_remaining_msec;
	unsigned long force_flag;
} TW_Lock;

/* GetParam descriptor */
typedef struct {
	unsigned short	table_id;
	unsigned short	parameter_id;
	unsigned short	parameter_size_bytes;
	unsigned short  actual_parameter_size_bytes;
	unsigned char	data[1];
} TW_Param_Apache, *PTW_Param_Apache;

/* Response queue */
typedef union TAG_TW_Response_Queue {
	u32 response_id;
	u32 value;
} TW_Response_Queue;

typedef struct TAG_TW_Info {
	char *buffer;
	int length;
	int offset;
	int position;
} TW_Info;

/* Compatibility information structure */
typedef struct TAG_TW_Compatibility_Info
{
	char driver_version[32];
	unsigned short working_srl;
	unsigned short working_branch;
	unsigned short working_build;
} TW_Compatibility_Info;

typedef struct TAG_TW_Device_Extension {
	u32                     *base_addr;
	unsigned long	       	*generic_buffer_virt[TW_Q_LENGTH];
	unsigned long	       	generic_buffer_phys[TW_Q_LENGTH];
	TW_Command_Full	       	*command_packet_virt[TW_Q_LENGTH];
	unsigned long		command_packet_phys[TW_Q_LENGTH];
	struct pci_dev		*tw_pci_dev;
	struct scsi_cmnd	*srb[TW_Q_LENGTH];
	unsigned char		free_queue[TW_Q_LENGTH];
	unsigned char		free_head;
	unsigned char		free_tail;
	unsigned char		pending_queue[TW_Q_LENGTH];
	unsigned char		pending_head;
	unsigned char		pending_tail;
	int     		state[TW_Q_LENGTH];
	unsigned int		posted_request_count;
	unsigned int		max_posted_request_count;
	unsigned int	        pending_request_count;
	unsigned int		max_pending_request_count;
	unsigned int		max_sgl_entries;
	unsigned int		sgl_entries;
	unsigned int		num_aborts;
	unsigned int		num_resets;
	unsigned int		sector_count;
	unsigned int		max_sector_count;
	unsigned int		aen_count;
	struct Scsi_Host	*host;
	long			flags;
	int			reset_print;
	TW_Event                *event_queue[TW_Q_LENGTH];
	unsigned char           error_index;
	unsigned char		event_queue_wrapped;
	unsigned int            error_sequence_id;
	int                     ioctl_sem_lock;
	u32                     ioctl_msec;
	int			chrdev_request_id;
	wait_queue_head_t	ioctl_wqueue;
	struct semaphore	ioctl_sem;
	char			aen_clobber;
	unsigned short		working_srl;
	unsigned short		working_branch;
	unsigned short		working_build;
} TW_Device_Extension;

#pragma pack()

#endif /* _3W_9XXX_H */