esp.h

Linux Kernel 2.6.9 for OMAP1710

/* $Id: esp.h,v 1.29 2001/12/11 04:55:47 davem Exp $
 * esp.h:  Defines and structures for the Sparc ESP (Enhanced SCSI
 *         Processor) driver under Linux.
 *
 * Copyright (C) 1995 David S. Miller ([e-mail])
 */

#ifndef _SPARC_ESP_H
#define _SPARC_ESP_H

/* For dvma controller register definitions. */
#include <asm/dma.h>

/* The ESP SCSI controllers have their register sets in three
 * "classes":
 *
 * 1) Registers which are both read and write.
 * 2) Registers which are read only.
 * 3) Registers which are write only.
 *
 * Yet, they all live within the same IO space.
 */

/* All the ESP registers are one byte each and are accessed longwords
 * apart with a big-endian ordering to the bytes.
 */
					/* Access    Description              Offset */
#define ESP_TCLOW	0x00UL		/* rw  Low bits of the transfer count 0x00   */
#define ESP_TCMED	0x04UL		/* rw  Mid bits of the transfer count 0x04   */
#define ESP_FDATA	0x08UL		/* rw  FIFO data bits                 0x08   */
#define ESP_CMD		0x0cUL		/* rw  SCSI command bits              0x0c   */
#define ESP_STATUS	0x10UL		/* ro  ESP status register            0x10   */
#define ESP_BUSID	ESP_STATUS	/* wo  Bus ID for select/reselect     0x10   */
#define ESP_INTRPT	0x14UL		/* ro  Kind of interrupt              0x14   */
#define ESP_TIMEO	ESP_INTRPT	/* wo  Timeout value for select/resel 0x14   */
#define ESP_SSTEP	0x18UL		/* ro  Sequence step register         0x18   */
#define ESP_STP		ESP_SSTEP	/* wo  Transfer period per sync       0x18   */
#define ESP_FFLAGS	0x1cUL		/* ro  Bits of current FIFO info      0x1c   */
#define ESP_SOFF	ESP_FFLAGS	/* wo  Sync offset                    0x1c   */
#define ESP_CFG1	0x20UL		/* rw  First configuration register   0x20   */
#define ESP_CFACT	0x24UL		/* wo  Clock conversion factor        0x24   */
#define ESP_STATUS2	ESP_CFACT	/* ro  HME status2 register           0x24   */
#define ESP_CTEST	0x28UL		/* wo  Chip test register             0x28   */
#define ESP_CFG2	0x2cUL		/* rw  Second configuration register  0x2c   */
#define ESP_CFG3	0x30UL		/* rw  Third configuration register   0x30   */
#define ESP_TCHI	0x38UL		/* rw  High bits of transfer count    0x38   */
#define ESP_UID		ESP_TCHI	/* ro  Unique ID code                 0x38   */
#define FAS_RLO		ESP_TCHI	/* rw  HME extended counter           0x38   */
#define ESP_FGRND	0x3cUL		/* rw  Data base for fifo             0x3c   */
#define FAS_RHI		ESP_FGRND	/* rw  HME extended counter           0x3c   */
#define ESP_REG_SIZE	0x40UL

/* Various revisions of the ESP board. */
enum esp_rev {
	esp100     = 0x00,  /* NCR53C90 - very broken */
	esp100a    = 0x01,  /* NCR53C90A */
	esp236     = 0x02,
	fas236     = 0x03,
	fas100a    = 0x04,
	fast       = 0x05,
	fashme     = 0x06,
	espunknown = 0x07
};

/* We allocate one of these for each scsi device and attach it to
 * SDptr->hostdata for use in the driver
 */
struct esp_device {
  unsigned char sync_min_period;
  unsigned char sync_max_offset;
  unsigned sync:1;
  unsigned wide:1;
  unsigned disconnect:1;
};

struct scsi_cmnd;

/* We get one of these for each ESP probed. */
struct esp {
	void __iomem		*eregs;		/* ESP controller registers */
	void __iomem		*dregs;		/* DMA controller registers */
	struct sbus_dma		*dma;		/* DMA controller sw state */
	struct Scsi_Host	*ehost;		/* Backpointer to SCSI Host */
	struct sbus_dev		*sdev;		/* Pointer to SBus entry */

	/* ESP Configuration Registers */
	u8			config1;	/* Copy of the 1st config register */
	u8			config2;	/* Copy of the 2nd config register */
	u8			config3[16];	/* Copy of the 3rd config register */

	/* The current command we are sending to the ESP chip.  This esp_command
	 * ptr needs to be mapped in DVMA area so we can send commands and read
	 * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
	 * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
	 * only send out 6, 10, and 12 byte SCSI commands, others we need to send
	 * one byte at a time.  esp_slowcmd being set says that we are doing one
	 * of the command types ESP doesn't understand, esp_scmdp keeps track of
	 * which byte we are sending, esp_scmdleft says how many bytes to go.
	 */
	volatile u8		*esp_command;    /* Location of command (CPU view)  */
	__u32			esp_command_dvma;/* Location of command (DVMA view) */
	unsigned char		esp_clen;	 /* Length of this command */
	unsigned char		esp_slowcmd;
	unsigned char		*esp_scmdp;
	unsigned char		esp_scmdleft;

	/* The following are used to determine the cause of an IRQ. Upon every
	 * IRQ entry we synchronize these with the hardware registers.
	 */
	u8			ireg;		/* Copy of ESP interrupt register */
	u8			sreg;		/* Copy of ESP status register */
	u8			seqreg;		/* Copy of ESP sequence step register */
	u8			sreg2;		/* Copy of HME status2 register */

	/* To save register writes to the ESP, which can be expensive, we
	 * keep track of the previous value that various registers had for
	 * the last target we connected to.  If they are the same for the
	 * current target, we skip the register writes as they are not needed.
	 */
	u8			prev_soff, prev_stp;
	u8			prev_cfg3, __cache_pad;

	/* We also keep a cache of the previous FAS/HME DMA CSR register value.  */
	u32			prev_hme_dmacsr;

	/* The HME is the biggest piece of shit I have ever seen. */
	u8			hme_fifo_workaround_buffer[16 * 2];
	u8			hme_fifo_workaround_count;

	/* For each target we keep track of save/restore data
	 * pointer information.  This needs to be updated majorly
	 * when we add support for tagged queueing.  -DaveM
	 */
	struct esp_pointers {
		char			*saved_ptr;
		struct scatterlist	*saved_buffer;
		int			saved_this_residual;
		int			saved_buffers_residual;
	} data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;

	/* Clock periods, frequencies, synchronization, etc. */
	unsigned int		cfreq;		/* Clock frequency in HZ */
	unsigned int		cfact;		/* Clock conversion factor */
	unsigned int		raw_cfact;	/* Raw copy from probing */
	unsigned int		ccycle;		/* One ESP clock cycle */
	unsigned int		ctick;		/* One ESP clock time */
	unsigned int		radelay;	/* FAST chip req/ack delay */
	unsigned int		neg_defp;	/* Default negotiation period */
	unsigned int		sync_defp;	/* Default sync transfer period */
	unsigned int		max_period;	/* longest our period can be */
	unsigned int		min_period;	/* shortest period we can withstand */

	struct esp		*next;		/* Next ESP we probed or NULL */
	char			prom_name[64];	/* Name of ESP device from prom */
	int			prom_node;	/* Prom node where ESP found */
	int			esp_id;		/* Unique per-ESP ID number */

	/* For slow to medium speed input clock rates we shoot for 5mb/s,
	 * but for high input clock rates we try to do 10mb/s although I
	 * don't think a transfer can even run that fast with an ESP even
	 * with DMA2 scatter gather pipelining.
	 */
#define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
#define SYNC_DEFP_FAST            0x19   /* 10mb/s */

	unsigned int		snip;		/* Sync. negotiation in progress */
	unsigned int		wnip;		/* WIDE negotiation in progress */
	unsigned int		targets_present;/* targets spoken to before */

	int		current_transfer_size;	/* Set at beginning of data dma */

	u8			espcmdlog[32];	/* Log of current esp cmds sent. */
	u8			espcmdent;	/* Current entry in esp cmd log. */

	/* Misc. info about this ESP */
	enum esp_rev		erev;		/* ESP revision */
	int			irq;		/* SBus IRQ for this ESP */
	int			scsi_id;	/* Who am I as initiator? */
	int			scsi_id_mask;	/* Bitmask of 'me'. */
	int			diff;		/* Differential SCSI bus? */
	int			bursts;		/* Burst sizes our DVMA supports */

	/* Our command queues, only one cmd lives in the current_SC queue. */
	struct scsi_cmnd	*issue_SC;	/* Commands to be issued */
	struct scsi_cmnd	*current_SC;	/* Who is currently working the bus */
	struct scsi_cmnd	*disconnected_SC;/* Commands disconnected from the bus */

	/* Message goo */
	u8			cur_msgout[16];
	u8			cur_msgin[16];
	u8			prevmsgout, prevmsgin;
	u8			msgout_len, msgin_len;
	u8			msgout_ctr, msgin_ctr;

	/* States that we cannot keep in the per cmd structure because they
	 * cannot be assosciated with any specific command.
	 */
	u8			resetting_bus;
	wait_queue_head_t	reset_queue;
};

/* Bitfield meanings for the above registers. */

/* ESP config reg 1, read-write, found on all ESP chips */
#define ESP_CONFIG1_ID        0x07             /* My BUS ID bits */
#define ESP_CONFIG1_CHTEST    0x08             /* Enable ESP chip tests */