ncr53c9x.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 671 行 · 第 1/3 页

#define esp_cfg3    io_addr + (12<<(esp->shift)) /* rw  Third configuration register   0x30  */
#define esp_cfg4    io_addr + (13<<(esp->shift)) /* rw  Fourth configuration register  0x34  */

    /* The following is found on all chips except the NCR53C90 (ESP100) */
#define esp_tchi    io_addr + (14<<(esp->shift)) /* rw  High bits of transfer count    0x38  */
#define esp_uid     esp_tchi                     /* ro  Unique ID code                 0x38  */
#define esp_fgrnd   io_addr + (15<<(esp->shift)) /* rw  Data base for fifo             0x3c  */
};

#endif

#else /* !defined(__i386__) && !defined(__x86_64__) */

#define esp_write(__reg, __val) outb((__val), (__reg))
#define esp_read(__reg) inb((__reg))

struct ESP_regs {
    unsigned int io_addr;
                                 /* Access    Description              Offset */
#define esp_tclow   io_addr      /* rw  Low bits of the transfer count 0x00   */
#define esp_tcmed   io_addr + 1  /* rw  Mid bits of the transfer count 0x04   */
#define esp_fdata   io_addr + 2  /* rw  FIFO data bits                 0x08   */
#define esp_cmnd    io_addr + 3  /* rw  SCSI command bits              0x0c   */
#define esp_status  io_addr + 4  /* ro  ESP status register            0x10   */
#define esp_busid   esp_status   /* wo  Bus ID for select/reselect     0x10   */
#define esp_intrpt  io_addr + 5  /* ro  Kind of interrupt              0x14   */
#define esp_timeo   esp_intrpt   /* wo  Timeout value for select/resel 0x14   */
#define esp_sstep   io_addr + 6  /* ro  Sequence step register         0x18   */
#define esp_stp     esp_sstep    /* wo  Transfer period per sync       0x18   */
#define esp_fflags  io_addr + 7  /* ro  Bits of current FIFO info      0x1c   */
#define esp_soff    esp_fflags   /* wo  Sync offset                    0x1c   */
#define esp_cfg1    io_addr + 8  /* rw  First configuration register   0x20   */
#define esp_cfact   io_addr + 9  /* wo  Clock conversion factor        0x24   */
#define esp_ctest   io_addr + 10 /* wo  Chip test register             0x28   */
#define esp_cfg2    io_addr + 11 /* rw  Second configuration register  0x2c   */

    /* The following is only found on the 53C9X series SCSI chips */
#define esp_cfg3    io_addr + 12 /* rw  Third configuration register   0x30  */
#define esp_cfg4    io_addr + 13 /* rw  Fourth configuration register  0x34  */

    /* The following is found on all chips except the NCR53C90 (ESP100) */
#define esp_tchi    io_addr + 14 /* rw  High bits of transfer count    0x38  */
#define esp_uid     esp_tchi     /* ro  Unique ID code                 0x38  */
#define esp_fgrnd   io_addr + 15 /* rw  Data base for fifo             0x3c  */
};

#endif /* !defined(__i386__) && !defined(__x86_64__) */

/* Various revisions of the ESP board. */
enum esp_rev {
  esp100     = 0x00,  /* NCR53C90 - very broken */
  esp100a    = 0x01,  /* NCR53C90A */
  esp236     = 0x02,
  fas236     = 0x03,
  fas100a    = 0x04,
  fast       = 0x05,
  fas366     = 0x06,
  fas216     = 0x07,
  fsc        = 0x08,  /* SYM53C94-2 */
  espunknown = 0x09
};

/* We allocate one of these for each scsi device and attach it to
 * SDptr->hostdata for use in the driver
 */
struct esp_device {
  unsigned char sync_min_period;
  unsigned char sync_max_offset;
  unsigned sync:1;
  unsigned wide:1;
  unsigned disconnect:1;
};

/* We get one of these for each ESP probed. */
struct NCR_ESP {
  struct NCR_ESP *next;                   /* Next ESP on probed or NULL */
  struct ESP_regs *eregs;	          /* All esp registers */
  int dma;                                /* Who I do transfers with. */
  void *dregs;		  		  /* And his registers. */
  struct Scsi_Host *ehost;                /* Backpointer to SCSI Host */

  void *edev;        		          /* Pointer to controller base/SBus */
  int esp_id;                             /* Unique per-ESP ID number */

  /* ESP Configuration Registers */
  unsigned char config1;                  /* Copy of the 1st config register */
  unsigned char config2;                  /* Copy of the 2nd config register */
  unsigned char config3[16];              /* Copy of the 3rd config register */

  /* The current command we are sending to the ESP chip.  This esp_command
   * ptr needs to be mapped in DVMA area so we can send commands and read
   * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
   * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
   * only send out 6, 10, and 12 byte SCSI commands, others we need to send
   * one byte at a time.  esp_slowcmd being set says that we are doing one
   * of the command types ESP doesn't understand, esp_scmdp keeps track of
   * which byte we are sending, esp_scmdleft says how many bytes to go.
   */
  volatile unchar *esp_command;           /* Location of command (CPU view)  */
  __u32            esp_command_dvma;      /* Location of command (DVMA view) */
  unsigned char esp_clen;                 /* Length of this command */
  unsigned char esp_slowcmd;
  unsigned char *esp_scmdp;
  unsigned char esp_scmdleft;

  /* The following are used to determine the cause of an IRQ. Upon every
   * IRQ entry we synchronize these with the hardware registers.
   */
  unchar ireg;                            /* Copy of ESP interrupt register */
  unchar sreg;                            /* Same for ESP status register */
  unchar seqreg;                          /* The ESP sequence register */

  /* The following is set when a premature interrupt condition is detected
   * in some FAS revisions.
   */
  unchar fas_premature_intr_workaround;

  /* To save register writes to the ESP, which can be expensive, we
   * keep track of the previous value that various registers had for
   * the last target we connected to.  If they are the same for the
   * current target, we skip the register writes as they are not needed.
   */
  unchar prev_soff, prev_stp, prev_cfg3;

  /* For each target we keep track of save/restore data
   * pointer information.  This needs to be updated majorly
   * when we add support for tagged queueing.  -DaveM
   */
  struct esp_pointers {
	  char *saved_ptr;
	  struct scatterlist *saved_buffer;
	  int saved_this_residual;
	  int saved_buffers_residual;
  } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;

  /* Clock periods, frequencies, synchronization, etc. */
  unsigned int cfreq;                    /* Clock frequency in HZ */
  unsigned int cfact;                    /* Clock conversion factor */
  unsigned int ccycle;                   /* One ESP clock cycle */
  unsigned int ctick;                    /* One ESP clock time */
  unsigned int radelay;                  /* FAST chip req/ack delay */
  unsigned int neg_defp;                 /* Default negotiation period */
  unsigned int sync_defp;                /* Default sync transfer period */
  unsigned int max_period;               /* longest our period can be */
  unsigned int min_period;               /* shortest period we can withstand */
  /* For slow to medium speed input clock rates we shoot for 5mb/s,
   * but for high input clock rates we try to do 10mb/s although I
   * don't think a transfer can even run that fast with an ESP even
   * with DMA2 scatter gather pipelining.
   */
#define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
#define SYNC_DEFP_FAST            0x19   /* 10mb/s */

  unsigned int snip;                      /* Sync. negotiation in progress */
  unsigned int wnip;                      /* WIDE negotiation in progress */
  unsigned int targets_present;           /* targets spoken to before */

  int current_transfer_size;              /* Set at beginning of data dma */

  unchar espcmdlog[32];                   /* Log of current esp cmds sent. */
  unchar espcmdent;                       /* Current entry in esp cmd log. */

  /* Misc. info about this ESP */
  enum esp_rev erev;                      /* ESP revision */
  int irq;                                /* IRQ for this ESP */
  int scsi_id;                            /* Who am I as initiator? */
  int scsi_id_mask;                       /* Bitmask of 'me'. */
  int diff;                               /* Differential SCSI bus? */
  int slot;                               /* Slot the adapter occupies */

  /* Our command queues, only one cmd lives in the current_SC queue. */
  Scsi_Cmnd *issue_SC;           /* Commands to be issued */
  Scsi_Cmnd *current_SC;         /* Who is currently working the bus */
  Scsi_Cmnd *disconnected_SC;    /* Commands disconnected from the bus */

  /* Message goo */
  unchar cur_msgout[16];
  unchar cur_msgin[16];
  unchar prevmsgout, prevmsgin;
  unchar msgout_len, msgin_len;
  unchar msgout_ctr, msgin_ctr;

  /* States that we cannot keep in the per cmd structure because they
   * cannot be assosciated with any specific command.
   */
  unchar resetting_bus;
  wait_queue_head_t reset_queue;

  unchar do_pio_cmds;		/* Do command transfer with pio */

  /* How much bits do we have to shift the registers */
  unsigned char shift;

  /* Functions handling DMA
   */ 
  /* Required functions */
  int  (*dma_bytes_sent)(struct NCR_ESP *, int);
  int  (*dma_can_transfer)(struct NCR_ESP *, Scsi_Cmnd *);
  void (*dma_dump_state)(struct NCR_ESP *);
  void (*dma_init_read)(struct NCR_ESP *, __u32, int);
  void (*dma_init_write)(struct NCR_ESP *, __u32, int);
  void (*dma_ints_off)(struct NCR_ESP *);
  void (*dma_ints_on)(struct NCR_ESP *);
  int  (*dma_irq_p)(struct NCR_ESP *);
  int  (*dma_ports_p)(struct NCR_ESP *);
  void (*dma_setup)(struct NCR_ESP *, __u32, int, int);

  /* Optional functions (i.e. may be initialized to 0) */
  void (*dma_barrier)(struct NCR_ESP *);
  void (*dma_drain)(struct NCR_ESP *);
  void (*dma_invalidate)(struct NCR_ESP *);
  void (*dma_irq_entry)(struct NCR_ESP *);
  void (*dma_irq_exit)(struct NCR_ESP *);
  void (*dma_led_off)(struct NCR_ESP *);
  void (*dma_led_on)(struct NCR_ESP *);
  void (*dma_poll)(struct NCR_ESP *, unsigned char *);
  void (*dma_reset)(struct NCR_ESP *);
    
  /* Optional virtual DMA functions */
  void (*dma_mmu_get_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
  void (*dma_mmu_get_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
  void (*dma_mmu_release_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
  void (*dma_mmu_release_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
  void (*dma_advance_sg)(Scsi_Cmnd *);