rocket_int.h

来自「Linux Kernel 2.6.9 for OMAP1710」· C头文件 代码 · 共 1,297 行 · 第 1/3 页

Call:     sGetRxCnt(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   int: The number of data bytes in the Rx FIFO.
Comments: Byte read of count register is required to obtain Rx count.

*/
#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)

/***************************************************************************
Function: sGetTxCnt
Purpose:  Get the number of data bytes in the Tx FIFO
Call:     sGetTxCnt(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   Byte_t: The number of data bytes in the Tx FIFO.
Comments: Byte read of count register is required to obtain Tx count.

*/
#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)

/*****************************************************************************
Function: sGetTxRxDataIO
Purpose:  Get the I/O address of a channel's TxRx Data register
Call:     sGetTxRxDataIO(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   WordIO_t: I/O address of a channel's TxRx Data register
*/
#define sGetTxRxDataIO(ChP) (ChP)->TxRxData

/***************************************************************************
Function: sInitChanDefaults
Purpose:  Initialize a channel structure to it's default state.
Call:     sInitChanDefaults(ChP)
          CHANNEL_T *ChP; Ptr to the channel structure
Comments: This function must be called once for every channel structure
          that exists before any other SSCI calls can be made.

*/
#define sInitChanDefaults(ChP) \
do { \
   (ChP)->CtlP = NULLCTLPTR; \
   (ChP)->AiopNum = NULLAIOP; \
   (ChP)->ChanID = AIOPID_NULL; \
   (ChP)->ChanNum = NULLCHAN; \
} while (0)

/***************************************************************************
Function: sResetAiopByNum
Purpose:  Reset the AIOP by number
Call:     sResetAiopByNum(CTLP,AIOPNUM)
	CONTROLLER_T CTLP; Ptr to controller structure
	AIOPNUM; AIOP index 
*/
#define sResetAiopByNum(CTLP,AIOPNUM) \
do { \
   sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
   sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
} while (0)

/***************************************************************************
Function: sSendBreak
Purpose:  Send a transmit BREAK signal
Call:     sSendBreak(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSendBreak(ChP) \
do { \
   (ChP)->TxControl[3] |= SETBREAK; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetBaud
Purpose:  Set baud rate
Call:     sSetBaud(ChP,Divisor)
          CHANNEL_T *ChP; Ptr to channel structure
          Word_t Divisor; 16 bit baud rate divisor for channel
*/
#define sSetBaud(ChP,DIVISOR) \
do { \
   (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
   (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
} while (0)

/***************************************************************************
Function: sSetData7
Purpose:  Set data bits to 7
Call:     sSetData7(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetData7(ChP) \
do { \
   (ChP)->TxControl[2] &= ~DATA8BIT; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetData8
Purpose:  Set data bits to 8
Call:     sSetData8(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetData8(ChP) \
do { \
   (ChP)->TxControl[2] |= DATA8BIT; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetDTR
Purpose:  Set the DTR output
Call:     sSetDTR(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetDTR(ChP) \
do { \
   (ChP)->TxControl[3] |= SET_DTR; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetEvenParity
Purpose:  Set even parity
Call:     sSetEvenParity(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: Function sSetParity() can be used in place of functions sEnParity(),
          sDisParity(), sSetOddParity(), and sSetEvenParity().

Warnings: This function has no effect unless parity is enabled with function
          sEnParity().
*/
#define sSetEvenParity(ChP) \
do { \
   (ChP)->TxControl[2] |= EVEN_PAR; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetOddParity
Purpose:  Set odd parity
Call:     sSetOddParity(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: Function sSetParity() can be used in place of functions sEnParity(),
          sDisParity(), sSetOddParity(), and sSetEvenParity().

Warnings: This function has no effect unless parity is enabled with function
          sEnParity().
*/
#define sSetOddParity(ChP) \
do { \
   (ChP)->TxControl[2] &= ~EVEN_PAR; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetRTS
Purpose:  Set the RTS output
Call:     sSetRTS(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetRTS(ChP) \
do { \
   if ((ChP)->rtsToggle) break; \
   (ChP)->TxControl[3] |= SET_RTS; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetRxTrigger
Purpose:  Set the Rx FIFO trigger level
Call:     sSetRxProcessor(ChP,Level)
          CHANNEL_T *ChP; Ptr to channel structure
          Byte_t Level; Number of characters in Rx FIFO at which the
             interrupt will be generated.  Can be any of the following flags:

             TRIG_NO:   no trigger
             TRIG_1:    1 character in FIFO
             TRIG_1_2:  FIFO 1/2 full
             TRIG_7_8:  FIFO 7/8 full
Comments: An interrupt will be generated when the trigger level is reached
          only if function sEnInterrupt() has been called with flag
          RXINT_EN set.  The RXF_TRIG flag in the Interrupt Idenfification
          register will be set whenever the trigger level is reached
          regardless of the setting of RXINT_EN.

*/
#define sSetRxTrigger(ChP,LEVEL) \
do { \
   (ChP)->RxControl[2] &= ~TRIG_MASK; \
   (ChP)->RxControl[2] |= LEVEL; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetStop1
Purpose:  Set stop bits to 1
Call:     sSetStop1(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetStop1(ChP) \
do { \
   (ChP)->TxControl[2] &= ~STOP2; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetStop2
Purpose:  Set stop bits to 2
Call:     sSetStop2(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetStop2(ChP) \
do { \
   (ChP)->TxControl[2] |= STOP2; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sSetTxXOFFChar
Purpose:  Set the Tx XOFF flow control character
Call:     sSetTxXOFFChar(ChP,Ch)
          CHANNEL_T *ChP; Ptr to channel structure
          Byte_t Ch; The value to set the Tx XOFF character to
*/
#define sSetTxXOFFChar(ChP,CH) \
do { \
   (ChP)->R[0x07] = (CH); \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
} while (0)

/***************************************************************************
Function: sSetTxXONChar
Purpose:  Set the Tx XON flow control character
Call:     sSetTxXONChar(ChP,Ch)
          CHANNEL_T *ChP; Ptr to channel structure
          Byte_t Ch; The value to set the Tx XON character to
*/
#define sSetTxXONChar(ChP,CH) \
do { \
   (ChP)->R[0x0b] = (CH); \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
} while (0)

/***************************************************************************
Function: sStartRxProcessor
Purpose:  Start a channel's receive processor
Call:     sStartRxProcessor(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: This function is used to start a Rx processor after it was
          stopped with sStopRxProcessor() or sStopSWInFlowCtl().  It
          will restart both the Rx processor and software input flow control.

*/
#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])

/***************************************************************************
Function: sWriteTxByte
Purpose:  Write a transmit data byte to a channel.
          ByteIO_t io: Channel transmit register I/O address.  This can
                           be obtained with sGetTxRxDataIO().
          Byte_t Data; The transmit data byte.
Warnings: This function writes the data byte without checking to see if
          sMaxTxSize is exceeded in the Tx FIFO.
*/
#define sWriteTxByte(IO,DATA) sOutB(IO,DATA)

int sInitController(CONTROLLER_T * CtlP,
		    int CtlNum,
		    ByteIO_t MudbacIO,
		    ByteIO_t * AiopIOList,
		    int AiopIOListSize,
		    int IRQNum, Byte_t Frequency, int PeriodicOnly);

int sPCIInitController(CONTROLLER_T * CtlP,
		       int CtlNum,
		       ByteIO_t * AiopIOList,
		       int AiopIOListSize,
		       WordIO_t ConfigIO,
		       int IRQNum,
		       Byte_t Frequency,
		       int PeriodicOnly,
		       int altChanRingIndicator, int UPCIRingInd);

int sReadAiopID(ByteIO_t io);
int sReadAiopNumChan(WordIO_t io);
int sInitChan(CONTROLLER_T * CtlP,
	      CHANNEL_T * ChP, int AiopNum, int ChanNum);
Byte_t sGetRxErrStatus(CHANNEL_T * ChP);
void sStopRxProcessor(CHANNEL_T * ChP);
void sStopSWInFlowCtl(CHANNEL_T * ChP);
void sFlushRxFIFO(CHANNEL_T * ChP);
void sFlushTxFIFO(CHANNEL_T * ChP);
int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);

extern Byte_t R[RDATASIZE];
extern CONTROLLER_T sController[CTL_SIZE];
extern Byte_t sIRQMap[16];
extern Byte_t sBitMapClrTbl[8];
extern Byte_t sBitMapSetTbl[8];
extern int sClockPrescale;

/*
 * Begin Linux specific definitions for the Rocketport driver
 *
 * This code is Copyright Theodore Ts'o, 1995-1997
 */

struct r_port {
	int magic;
	int line;
	int flags;
	int count;
	int blocked_open;
	struct tty_struct *tty;
	unsigned int board:3;
	unsigned int aiop:2;
	unsigned int chan:3;
	CONTROLLER_t *ctlp;
	CHANNEL_t channel;
	int closing_wait;
	int close_delay;
	int intmask;
	int xmit_fifo_room;	/* room in xmit fifo */
	unsigned char *xmit_buf;
	int xmit_head;
	int xmit_tail;
	int xmit_cnt;
	int session;
	int pgrp;
	int cd_status;
	int ignore_status_mask;
	int read_status_mask;
	int cps;

#ifdef DECLARE_WAITQUEUE
	wait_queue_head_t open_wait;
	wait_queue_head_t close_wait;
#else
	struct wait_queue *open_wait;
	struct wait_queue *close_wait;
#endif
	spinlock_t slock;
	struct semaphore write_sem;
};

#define RPORT_MAGIC 0x525001

#define NUM_BOARDS 8
#define MAX_RP_PORTS (32*NUM_BOARDS)

/*
 * The size of the xmit buffer is 1 page, or 4096 bytes
 */
#define XMIT_BUF_SIZE 4096

/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS 256

/* Internal flags used only by the rocketport driver */
#define ROCKET_INITIALIZED	0x80000000	/* Port is active */
#define ROCKET_CLOSING		0x40000000	/* Serial port is closing */
#define ROCKET_NORMAL_ACTIVE	0x20000000	/* Normal port is active */

/* tty subtypes */
#define SERIAL_TYPE_NORMAL 1

/*
 * Assigned major numbers for the Comtrol Rocketport
 */
#define TTY_ROCKET_MAJOR	46
#define CUA_ROCKET_MAJOR	47

#ifdef PCI_VENDOR_ID_RP
#undef PCI_VENDOR_ID_RP
#undef PCI_DEVICE_ID_RP8OCTA
#undef PCI_DEVICE_ID_RP8INTF
#undef PCI_DEVICE_ID_RP16INTF
#undef PCI_DEVICE_ID_RP32INTF
#undef PCI_DEVICE_ID_URP8OCTA
#undef PCI_DEVICE_ID_URP8INTF
#undef PCI_DEVICE_ID_URP16INTF
#undef PCI_DEVICE_ID_CRP16INTF
#undef PCI_DEVICE_ID_URP32INTF
#endif

/*  Comtrol PCI Vendor ID */
#define PCI_VENDOR_ID_RP		0x11fe

/*  Comtrol Device ID's */
#define PCI_DEVICE_ID_RP32INTF		0x0001	/* Rocketport 32 port w/external I/F     */
#define PCI_DEVICE_ID_RP8INTF		0x0002	/* Rocketport 8 port w/external I/F      */
#define PCI_DEVICE_ID_RP16INTF		0x0003	/* Rocketport 16 port w/external I/F     */
#define PCI_DEVICE_ID_RP4QUAD		0x0004	/* Rocketport 4 port w/quad cable        */
#define PCI_DEVICE_ID_RP8OCTA		0x0005	/* Rocketport 8 port w/octa cable        */
#define PCI_DEVICE_ID_RP8J		0x0006	/* Rocketport 8 port w/RJ11 connectors   */
#define PCI_DEVICE_ID_RP4J		0x0007	/* Rocketport 4 port w/RJ11 connectors   */
#define PCI_DEVICE_ID_RP8SNI		0x0008	/* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
#define PCI_DEVICE_ID_RP16SNI		0x0009	/* Rocketport 16 port w/ DB78 SNI (Siemens) connector   */
#define PCI_DEVICE_ID_RPP4		0x000A	/* Rocketport Plus 4 port                */
#define PCI_DEVICE_ID_RPP8		0x000B	/* Rocketport Plus 8 port                */
#define PCI_DEVICE_ID_RP6M		0x000C	/* RocketModem 6 port                    */
#define PCI_DEVICE_ID_RP4M		0x000D	/* RocketModem 4 port                    */
#define PCI_DEVICE_ID_RP2_232           0x000E	/* Rocketport Plus 2 port RS232          */
#define PCI_DEVICE_ID_RP2_422           0x000F	/* Rocketport Plus 2 port RS422          */ 

/* Universal PCI boards  */
#define PCI_DEVICE_ID_URP32INTF		0x0801	/* Rocketport UPCI 32 port w/external I/F */ 
#define PCI_DEVICE_ID_URP8INTF		0x0802	/* Rocketport UPCI 8 port w/external I/F  */
#define PCI_DEVICE_ID_URP16INTF		0x0803	/* Rocketport UPCI 16 port w/external I/F */
#define PCI_DEVICE_ID_URP8OCTA		0x0805	/* Rocketport UPCI 8 port w/octa cable    */
#define PCI_DEVICE_ID_UPCI_RM3_8PORT    0x080C	/* Rocketmodem III 8 port                 */
#define PCI_DEVICE_ID_UPCI_RM3_4PORT    0x080D	/* Rocketmodem III 4 port                 */

/* Compact PCI device */ 
#define PCI_DEVICE_ID_CRP16INTF		0x0903	/* Rocketport Compact PCI 16 port w/external I/F */

#define TTY_GET_LINE(t) t->index
#define TTY_DRIVER_MINOR_START(t) t->driver->minor_start
#define TTY_DRIVER_SUBTYPE(t) t->driver->subtype
#define TTY_DRIVER_NAME(t) t->driver->name
#define TTY_DRIVER_NAME_BASE(t) t->driver->name_base
#define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer
#define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t)