omap24xxcam.h

Linux Kernel 2.6.9 for OMAP1710

#define DISPC_CONTROL			0x040
#define DISPC_CONFIG			0x044
#define DISPC_CAPABLE			0x048
#define DISPC_DEFAULT_COLOR0		0x04C
#define DISPC_DEFAULT_COLOR1		0x050
#define DISPC_TRANS_COLOR0		0x054
#define DISPC_TRANS_COLOR1		0x058
#define DISPC_LINE_STATUS		0x05C
#define DISPC_LINE_NUMBER		0x060
#define DISPC_TIMING_H			0x064
#define DISPC_TIMING_V			0x068
#define DISPC_POL_FREQ			0x06C
#define DISPC_DIVISOR			0x070
#define DISPC_SIZE_DIG			0x078
#define DISPC_SIZE_LCD			0x07C
#define DISPC_GFX_BA0			0x080
#define DISPC_GFX_BA1			0x084
#define DISPC_GFX_POSITION		0x088
#define DISPC_GFX_SIZE			0x08C
#define DISPC_GFX_ATTRIBUTES		0x0A0
#define DISPC_GFX_FIFO_THRESHOLD	0x0A4
#define DISPC_GFX_FIFO_SIZE		0x0A8
#define DISPC_GFX_ROW_INC		0x0AC
#define DISPC_GFX_PIXEL_INC		0x0B0
#define DISPC_GFX_WINDOW_SKIP		0x0B4
#define DISPC_GFX_TABLE_BA		0x0B8

/* The registers for the video pipelines are parameterized by the video pipeline
 * index: n=0 for VID1 and n=1 for VID2.
 */
#define DISPC_VID_BA0(n)		(0x0BC + (n)*0x90)
#define DISPC_VID_BA1(n)		(0x0C0 + (n)*0x90)
#define DISPC_VID_POSITION(n)		(0x0C4 + (n)*0x90)
#define DISPC_VID_SIZE(n)		(0x0C8 + (n)*0x90)
#define DISPC_VID_ATTRIBUTES(n)		(0x0CC + (n)*0x90)
#define DISPC_VID_FIFO_THRESHOLD(n)	(0x0D0 + (n)*0x90)
#define DISPC_VID_FIFO_SIZE(n)		(0x0D4 + (n)*0x90)
#define DISPC_VID_ROW_INC(n)		(0x0D8 + (n)*0x90)
#define DISPC_VID_PIXEL_INC(n)		(0x0DC + (n)*0x90)
#define DISPC_VID_FIR(n)		(0x0E0 + (n)*0x90)
#define DISPC_VID_PICTURE_SIZE(n)	(0x0E4 + (n)*0x90)
#define DISPC_VID_ACCU0(n)		(0x0E8 + (n)*0x90)
#define DISPC_VID_ACCU1(n)		(0x0EC + (n)*0x90)
/* The FIR coefficients are parameterized by the video pipeline index n = {0, 1}
 * and the coefficient index i = {0, 1, 2, 3, 4, 5, 6, 7}.
 */
#define DISPC_VID_FIR_COEF_H(n, i)	(0x0F0 + (i)*0x8 + (n)*0x90)
#define DISPC_VID_FIR_COEF_HV(n, i)	(0x0F4 + (i)*0x8 + (n)*0x90)
#define DISPC_VID_CONV_COEF0(n)		(0x130 + (n)*0x90)
#define DISPC_VID_CONV_COEF1(n)		(0x134 + (n)*0x90)
#define DISPC_VID_CONV_COEF2(n)		(0x138 + (n)*0x90)
#define DISPC_VID_CONV_COEF3(n)		(0x13C + (n)*0x90)
#define DISPC_VID_CONV_COEF4(n)		(0x140 + (n)*0x90)

/* Define bit fields within selected registers */
#define DISPC_REVISION_MAJOR				(15 << 4)
#define DISPC_REVISION_MAJOR_SHIFT			4
#define DISPC_REVISION_MINOR				(15 << 0)
#define DISPC_REVISION_MINOR_SHIFT			0

#define DISPC_SYSCONFIG_MIDLEMODE			(3 << 12)
#define DISPC_SYSCONFIG_MIDLEMODE_FSTANDBY		(0 << 12)
#define DISPC_SYSCONFIG_MIDLEMODE_NSTANDBY		(1 << 12)
#define DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY		(2 << 12)
#define DISPC_SYSCONFIG_SIDLEMODE			(3 <<  3)
#define DISPC_SYSCONFIG_SIDLEMODE_FIDLE			(0 <<  3)
#define DISPC_SYSCONFIG_SIDLEMODE_NIDLE			(1 <<  3)
#define DISPC_SYSCONFIG_SIDLEMODE_SIDLE			(2 <<  3)
#define DISPC_SYSCONFIG_SOFTRESET			(1 <<  1)
#define DISPC_SYSCONFIG_AUTOIDLE			(1 <<  0)

#define DISPC_SYSSTATUS_RESETDONE			(1 << 0)

#define DISPC_IRQSTATUS_SYNCLOST			(1 << 14)
#define DISPC_IRQSTATUS_VID2ENDWINDOW			(1 << 13)
#define DISPC_IRQSTATUS_VID2FIFOUNDERFLOW		(1 << 12)
#define DISPC_IRQSTATUS_VID1ENDWINDOW			(1 << 11)
#define DISPC_IRQSTATUS_VID1FIFOUNDERFLOW		(1 << 10)
#define DISPC_IRQSTATUS_OCPERROR			(1 <<  9)
#define DISPC_IRQSTATUS_PALETTEGAMMALOADING		(1 <<  8)
#define DISPC_IRQSTATUS_GFXENDWINDOW			(1 <<  7)
#define DISPC_IRQSTATUS_GFXFIFOUNDERFLOW		(1 <<  6)
#define DISPC_IRQSTATUS_PROGRAMMEDLINENUMBER		(1 <<  5)
#define DISPC_IRQSTATUS_ACBIASCOUNTSTATUS		(1 <<  4)
#define DISPC_IRQSTATUS_EVSYNC_ODD			(1 <<  3)
#define DISPC_IRQSTATUS_EVSYNC_EVEN			(1 <<  2)
#define DISPC_IRQSTATUS_VSYNC				(1 <<  1)
#define DISPC_IRQSTATUS_FRAMEDONE			(1 <<  0)

#define DISPC_IRQENABLE_SYNCLOST			(1 << 14)
#define DISPC_IRQENABLE_VID2ENDWINDOW			(1 << 13)
#define DISPC_IRQENABLE_VID2FIFOUNDERFLOW		(1 << 12)
#define DISPC_IRQENABLE_VID1ENDWINDOW			(1 << 11)
#define DISPC_IRQENABLE_VID1FIFOUNDERFLOW		(1 << 10)
#define DISPC_IRQENABLE_OCPERROR			(1 <<  9)
#define DISPC_IRQENABLE_PALETTEGAMMALOADING		(1 <<  8)
#define DISPC_IRQENABLE_GFXENDWINDOW			(1 <<  7)
#define DISPC_IRQENABLE_GFXFIFOUNDERFLOW		(1 <<  6)
#define DISPC_IRQENABLE_PROGRAMMEDLINENUMBER		(1 <<  5)
#define DISPC_IRQENABLE_ACBIASCOUNTSTATUS		(1 <<  4)
#define DISPC_IRQENABLE_EVSYNC_ODD			(1 <<  3)
#define DISPC_IRQENABLE_EVSYNC_EVEN			(1 <<  2)
#define DISPC_IRQENABLE_VSYNC				(1 <<  1)
#define DISPC_IRQENABLE_FRAMEDONE			(1 <<  0)

#define DISPC_CONTROL_TDMUNUSEDBITS			(3 << 25)
#define DISPC_CONTROL_TDMUNUSEDBITS_LOWLEVEL		(0 << 25)
#define DISPC_CONTROL_TDMUNUSEDBITS_HIGHLEVEL		(1 << 25)
#define DISPC_CONTROL_TDMUNUSEDBITS_UNCHANGED		(2 << 25)
#define DISPC_CONTROL_TDMCYCLEFORMAT			(3 << 23)
#define DISPC_CONTROL_TDMCYCLEFORMAT_1CYCPERPIX		(0 << 23)
#define DISPC_CONTROL_TDMCYCLEFORMAT_2CYCPERPIX		(1 << 23)
#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPERPIX		(2 << 23)
#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPER2PIX	(3 << 23)
#define DISPC_CONTROL_TDMPARALLELMODE			(3 << 21)
#define DISPC_CONTROL_TDMPARALLELMODE_8BPARAINT		(0 << 21)
#define DISPC_CONTROL_TDMPARALLELMODE_9BPARAINT		(1 << 21)
#define DISPC_CONTROL_TDMPARALLELMODE_12BPARAINT	(2 << 21)
#define DISPC_CONTROL_TDMPARALLELMODE_16BPARAINT	(3 << 21)
#define DISPC_CONTROL_TDMENABLE				(1 << 20)
#define DISPC_CONTROL_HT				(7 << 17)
#define DISPC_CONTROL_HT_SHIFT				17
#define DISPC_CONTROL_GPOUT1				(1 << 16)
#define DISPC_CONTROL_GPOUT0				(1 << 15)
#define DISPC_CONTROL_GPIN1				(1 << 14)
#define DISPC_CONTROL_GPIN0				(1 << 13)
#define DISPC_CONTROL_OVERLAYOPTIMIZATION		(1 << 12)
#define DISPC_CONTROL_RFBIMODE				(1 << 11)
#define DISPC_CONTROL_SECURE				(1 << 10)
#define DISPC_CONTROL_TFTDATALINES			(3 <<  8)
#define DISPC_CONTROL_TFTDATALINES_OALSB12B		(0 <<  8)
#define DISPC_CONTROL_TFTDATALINES_OALSB16B		(1 <<  8)
#define DISPC_CONTROL_TFTDATALINES_OALSB18B		(2 <<  8)
#define DISPC_CONTROL_TFTDATALINES_OALSB24B		(3 <<  8)
#define DISPC_CONTROL_TFTDITHERENABLE			(1 <<  7)
#define DISPC_CONTROL_GODIGITAL				(1 <<  6)
#define DISPC_CONTROL_GOLCD				(1 <<  5)
#define DISPC_CONTROL_M8B				(1 <<  4)
#define DISPC_CONTROL_STNTFT				(1 <<  3)
#define DISPC_CONTROL_MONOCOLOR				(1 <<  2)
#define DISPC_CONTROL_DIGITALENABLE			(1 <<  1)
#define DISPC_CONTROL_LCDENABLE				(1 <<  0)

#define DISPC_CONFIG_TCKDIGSELECTION			(1 << 13)
#define DISPC_CONFIG_TCKDIGENABLE			(1 << 12)
#define DISPC_CONFIG_TCKLCDSELECTION			(1 << 11)
#define DISPC_CONFIG_TCKLCDENABLE			(1 << 10)
#define DISPC_CONFIG_FUNCGATED				(1 <<  9)
#define DISPC_CONFIG_ACBIASGATED			(1 <<  8)
#define DISPC_CONFIG_VSYNCGATED				(1 <<  7)
#define DISPC_CONFIG_HSYNCGATED				(1 <<  6)
#define DISPC_CONFIG_PIXELCLOCKGATED			(1 <<  5)
#define DISPC_CONFIG_PIXELDATAGATED			(1 <<  4)
#define DISPC_CONFIG_PALETTEGAMMATABLE			(1 <<  3)
#define DISPC_CONFIG_LOADMODE_FRDATLEFR			(1 <<  2)
#define DISPC_CONFIG_LOADMODE_PGTABUSETB		(1 <<  1)
#define DISPC_CONFIG_PIXELGATED				(1 <<  0)

#define DISPC_CAPABLE_GFXGAMMATABLECAPABLE		(1 <<  9)
#define DISPC_CAPABLE_GFXLAYERCAPABLE			(1 <<  8)
#define DISPC_CAPABLE_GFXTRANSDSTCAPABLE		(1 <<  7)
#define DISPC_CAPABLE_STNDITHERINGCAPABLE		(1 <<  6)
#define DISPC_CAPABLE_TFTDITHERINGCAPABLE		(1 <<  5)
#define DISPC_CAPABLE_VIDTRANSSRCCAPABLE		(1 <<  4)
#define DISPC_CAPABLE_VIDLAYERCAPABLE			(1 <<  3)
#define DISPC_CAPABLE_VIDVERTFIRCAPABLE			(1 <<  2)
#define DISPC_CAPABLE_VIDHORFIRCAPABLE			(1 <<  1)
#define DISPC_CAPABLE_VIDCAPABLE			(1 <<  0)

#define DISPC_POL_FREQ_ONOFF				(1 << 17)
#define DISPC_POL_FREQ_RF				(1 << 16)
#define DISPC_POL_FREQ_IEO				(1 << 15)
#define DISPC_POL_FREQ_IPC				(1 << 14)
#define DISPC_POL_FREQ_IHS				(1 << 13)
#define DISPC_POL_FREQ_IVS				(1 << 12)
#define DISPC_POL_FREQ_ACBI				(15 << 8)
#define DISPC_POL_FREQ_ACBI_SHIFT			8
#define DISPC_POL_FREQ_ACB				0xFF
#define DISPC_POL_FREQ_ACB_SHIFT			0

#define DISPC_TIMING_H_HBP				(0xFF << 20)
#define DISPC_TIMING_H_HBP_SHIFT			20
#define DISPC_TIMING_H_HFP				(0xFF << 8)
#define DISPC_TIMING_H_HFP_SHIFT			8
#define DISPC_TIMING_H_HSW				(0x3F << 0)
#define DISPC_TIMING_H_HSW_SHIFT			0

#define DISPC_TIMING_V_VBP				(0xFF << 20)
#define DISPC_TIMING_V_VBP_SHIFT			20
#define DISPC_TIMING_V_VFP				(0xFF << 8)
#define DISPC_TIMING_V_VFP_SHIFT			8
#define DISPC_TIMING_V_VSW				(0x3F << 0)
#define DISPC_TIMING_V_VSW_SHIFT			0

#define DISPC_DIVISOR_LCD				(0xFF << 16)
#define DISPC_DIVISOR_LCD_SHIFT				16
#define DISPC_DIVISOR_PCD				0xFF
#define DISPC_DIVISOR_PCD_SHIFT				0

#define DISPC_SIZE_LCD_LPP				(0x7FF << 16)
#define DISPC_SIZE_LCD_LPP_SHIFT			16
#define DISPC_SIZE_LCD_PPL				0x7FF
#define DISPC_SIZE_LCD_PPL_SHIFT			0

#define DISPC_SIZE_DIG_LPP				(0x7FF << 16)
#define DISPC_SIZE_DIG_LPP_SHIFT			16
#define DISPC_SIZE_DIG_PPL				0x7FF
#define DISPC_SIZE_DIG_PPL_SHIFT			0

#define DISPC_GFX_POSITION_GFXPOSY			(0x7FF << 16)
#define DISPC_GFX_POSITION_GFXPOSY_SHIFT		16
#define DISPC_GFX_POSITION_GFXPOSX			0x7FF
#define DISPC_GFX_POSITION_GFXPOSX_SHIFT		0

#define DISPC_GFX_SIZE_GFXSIZEY				(0x7FF << 16)
#define DISPC_GFX_SIZE_GFXSIZEY_SHIFT			16
#define DISPC_GFX_SIZE_GFXSIZEX				0x7FF
#define DISPC_GFX_SIZE_GFXSIZEX_SHIFT			0

#define DISPC_GFX_ATTRIBUTES_GFXENDIANNESS		(1 << 10)
#define DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE		(1 <<  9)
#define DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT		(1 <<  8)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE		(3 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST4X32	(0 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST8X32	(1 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST16X32	(2 <<  6)
#define DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE	(1 <<  5)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT			(15 << 1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1		(0 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2		(1 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4		(2 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8		(3 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12		(4 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16		(6 <<  1)
#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24		(8 <<  1)
#define DISPC_GFX_ATTRIBUTES_ENABLE			(1 <<  0)

#define DISPC_GFX_FIFO_THRESHOLD_HIGH			(0x1FF << 16)
#define DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT		16
#define DISPC_GFX_FIFO_THRESHOLD_LOW			0x1FF
#define DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT		0

#define DISPC_VID_POSITION_VIDPOSY			(0x7FF << 16)
#define DISPC_VID_POSITION_VIDPOSY_SHIFT		16
#define DISPC_VID_POSITION_VIDPOSX			0x7FF
#define DISPC_VID_POSITION_VIDPOSX_SHIFT		0

#define DISPC_VID_SIZE_VIDSIZEY				(0x7FF << 16)
#define DISPC_VID_SIZE_VIDSIZEY_SHIFT			16
#define DISPC_VID_SIZE_VIDSIZEX				0x7FF
#define DISPC_VID_SIZE_VIDSIZEX_SHIFT			0

#define DISPC_VID_ATTRIBUTES_VIDROWREPEATENABLE		(1 << 18)
#define DISPC_VID_ATTRIBUTES_VIDENDIANNESS		(1 << 17)
#define DISPC_VID_ATTRIBUTES_VIDCHANNELOUT		(1 << 16)
#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE		(3 << 14)
#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST4X32	(0 << 14)
#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST8X32	(1 << 14)
#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST16X32	(2 << 14)
#define DISPC_VID_ATTRIBUTES_VIDROTATION		(3 << 12)
#define DISPC_VID_ATTRIBUTES_VIDROTATION_NOROT		(0 << 12)
#define DISPC_VID_ATTRIBUTES_VIDROTATION_ROT90		(1 << 12)
#define DISPC_VID_ATTRIBUTES_VIDROTATION_ROT180		(2 << 12)
#define DISPC_VID_ATTRIBUTES_VIDROTATION_ROT270		(3 << 12)
#define DISPC_VID_ATTRIBUTES_VIDFULLRANGE		(1 << 11)
#define DISPC_VID_ATTRIBUTES_VIDREPLICATIONENABLE	(1 << 10)
#define DISPC_VID_ATTRIBUTES_VIDCOLORCONVENABLE		(1 <<  9)
#define DISPC_VID_ATTRIBUTES_VIDVRESIZECONF		(1 <<  8)
#define DISPC_VID_ATTRIBUTES_VIDHRESIZECONF		(1 <<  7)
#define DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_VRESIZE	(1 <<  6)
#define DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_HRESIZE	(1 <<  5)
#define DISPC_VID_ATTRIBUTES_VIDFORMAT			(15 << 1)
#define DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB16		(6  << 1)
#define DISPC_VID_ATTRIBUTES_VIDFORMAT_YUV2		(10 << 1)
#define DISPC_VID_ATTRIBUTES_VIDFORMAT_UYVY		(11 << 1)
#define DISPC_VID_ATTRIBUTES_ENABLE			(1 <<  0)

#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEY		(0x7FF << 16)
#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT	16
#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEX		0x7FF
#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT	0
#define VIDIOC_S_VID2          _IOWR ('V', 90, struct omap24xx_vid2_format)
#define VIDIOC_S_VID2_DISABLE     _IOWR ('V', 91, int)

#endif	/* ifndef OMAP24XXFB_H */

#endif	/* ifndef OMAP24XXCAM_H */